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US6091140A Expired / Lapsed US ⏱️ 0.0 years remaining

Thin chip-size integrated circuit package

Assignee: Texas Instruments Inc
•
Filing: 1998-10-23
•
Granted: 2000-07-18
•
Expires: 2018-10-23
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Abstract

Abstract In accordance with the present invention, there is provided an electrically insulating substrate having first and second surfaces, an outline and an opening. A plurality of electrically conductive routing strips is integral with the substrate. A plurality of contact pads is disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A semiconductor chip is adhered to the second surface of the substrate. The chip has an outline that is substantially the same as the outline of the substrate. The chip has at least one bonding pad. Wire bonding electrically connects the bonding pad to a routing strip. At least one bus bar is integral with the substrate. The bus bar is positioned remote from the substrate opening and is electrically connected to a bonding pad of the chip and to a contact pad disposed on the first surface of the substrate. At least one grounding pad is disposed on the first surface of the substrate, the grounding pad being electrically connected to at least one bus bar. Encapsulating material fills the opening and covers the wire bonding and the bonding pads. Solder balls are disposed on the contact pads positioned on the first surface of the substrate to enable attachment to wiring boards or other devices or applications. The overall profile of the integrated circuit package of the present invention is preferably about 0.78 mm.

Inventors

  • 👤 Tuck Fook Toh
  • 👤 Chew Weng Leong
  • 👤 Chee Kiang Yew
  • 👤 Pang Hup Ong

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 19:25
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W70/00; H10W70/40; H10W72/00; H10W72/071; H10W72/075; H10W72/07531; H10W72/07536; H10W72/07551; H10W72/07555; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5525; H10W72/5528; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 209 words
A semiconductor device comprising: an electrically insulating substrate having first and second surfaces, an outline and an opening; a plurality of electrically conductive routing strips integral with said substrate; a plurality of contact pads disposed on said first surface, at least one of said contact pads electrically connected with at least one of said routing strips; a semiconductor circuit chip adhered to said second surface of said substrate, said chip having an outline that is substantially the same as said outline of said substrate, said chip having at least one bonding pad; bonding wires electrically connecting said at least one bonding pad to at least one of said routing strips; at least one bus bar integral with said substrate, said at least one bus bar electrically connected to at least one of said contact pads and to at least one of said bonding pads; said at least one bus bar positioned remote from said opening; encapsulating material filling said opening to cover said bonding wires and said at least one bonding pad; and at least one solder ball disposed on at least one of said contact pads; wherein said at least one bus bar is positioned more remote from said at least one bonding pad than said contact pads.
Claim 2
Dependent Claim 209 words
A semiconductor device comprising: an electrically insulating substrate having first and second surfaces, an outline and an opening; a plurality of electrically conductive routing strips integral with said substrate; a plurality of contact pads disposed on said first surface, at least one of said contact pads electrically connected with at least one of said routing strips; a semiconductor circuit chip adhered to said second surface of said substrate, said chip having an outline that is substantially the same as said outline of said substrate, said chip having at least one bonding pad; bonding wires electrically connecting said at least one bonding pad to at least one of said routing strips; at least one bus bar integral with said substrate, said at least one bus bar electrically connected to at least one of said contact pads and to at least one of said bonding pads; said at least one bus bar positioned remote from said opening; encapsulating material filling said opening to cover said bonding wires and said at least one bonding pad; and at least one solder ball disposed on at least one of said contact pads; wherein said at least one bus bar is positioned more remote from said at least one bonding pad than said contact pads.
Claim 3
Dependent Claim 18 words
The semiconductor device according to claim 1 wherein the over profile of said device is about 0.78 mm.
Claim 4
Dependent Claim 29 words
The semiconductor device according to claim 1 wherein said at least one bus bar is electrically connected to at least one conductive routing strip being integral with said substrate.
Claim 5
Dependent Claim 16 words
The semiconductor device according to claim 1 wherein said routing strips are spaced about said opening.
Claim 6
Dependent Claim 25 words
The semiconductor device according to claim 1 wherein said encapsulating material has a thickness of between about 0.05 and 0.15 mm over said bonding wires.
Claim 7
Dependent Claim 22 words
The semiconductor device according to claim 1 wherein said encapsulating material has a thickness of about 0.1 mm over said bonding wires.
Claim 8
Dependent Claim 22 words
The semiconductor device of claim 1 wherein said at least one solder ball is between about 0.1 and 0.5 mm in diameter.
Claim 9
Dependent Claim 19 words
The semiconductor device of claim 1 wherein said at least one solder ball is about 0.2 mm in diameter.
Claim 10
Dependent Claim 20 words
The semiconductor device according to claim 1 wherein said chip has a thickness of between about 0.2 and 0.5 mm.
Claim 11
Dependent Claim 17 words
The semiconductor device according to claim 1 wherein said chip has a thickness of about 0.28 mm.
Claim 12
Dependent Claim 20 words
The semiconductor device according to claim 1 wherein said substrate has a thickness of between about 0.1 and 0.7 mm.
Claim 13
Dependent Claim 17 words
The semiconductor device according to claim 1 wherein said substrate has a thickness of about 0.2 mm.
Claim 14
Dependent Claim 21 words
The semiconductor device according to claim 1 wherein the overall profile of said device is between about 0.5 and 1.7 mm.

References Cited (Backward Citations)

US6013946A Cited
US5866949A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-07-18 2004-01-17 2004-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-07-18 2008-01-17 2008-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-07-18 2012-01-17 2012-07-18 $7700.00 Window Closed / Lapsed

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