US6087694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and fabrication method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1998-06-05
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Granted: 2000-07-11
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Expires: 2018-06-05
Abstract
Abstract A capacitor lower electrode is formed so as to be connected to a main surface of a silicon substrate. The capacitor lower electrode includes a plug portion, a bottom wall portion, and a vertical wall portion. An insulation layer for suppressing crystallization of the vertical wall portion is formed between the bottom wall portion and the vertical wall portion. A capacitor upper electrode is formed on the capacitor lower electrode with a capacitor dielectric layer therebetween.
Inventors
- 👤 Yoshikazu Ohno
- 👤 Yutaka Inaba
- 👤 Junichi Tsuchimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/716; H10D84/00; H10D84/01; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
67 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor during the corrugation process.
Claim 2
Dependent Claim
67 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor during the corrugation process.
Claim 3
Dependent Claim
31 words
The semiconductor memory device according to claim 1, wherein said crystallization suppress portion is formed of a layer of an insulation material with a thickness of not more than 3 nm.
Claim 4
Dependent Claim
46 words
The semiconductor memory device according to claim 1, wherein said crystallization suppress portion is formed of a compound of a material of said one electrode of a capacitor and at least one of nitrogen and oxygen, and has a thickness of not more than 3 nm.
Claim 5
Dependent Claim
112 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor; wherein said first conductor is a plug portion connected to said main surface, and wherein said second conductor includes a bottom wall portion formed on said plug portion with said crystallization suppress portion therebetween, and a vertical wall portion connected to a side surface of said bottom wall portion.
Claim 6
Dependent Claim
112 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor; wherein said first conductor is a plug portion connected to said main surface, and wherein said second conductor includes a bottom wall portion formed on said plug portion with said crystallization suppress portion therebetween, and a vertical wall portion connected to a side surface of said bottom wall portion.
Claim 7
Dependent Claim
112 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor; wherein said first conductor includes a plug portion connected to said main surface and a bottom wall portion formed on said plug portion, and wherein said second conductor is a vertical wall portion connected to a side surface of said bottom wall portion with said crystallization suppress portion therebetween.
Claim 8
Dependent Claim
112 words
A semiconductor memory device comprising: a semiconductor substrate having a main surface; one electrode of a capacitor having a surface subjected to a corrugation process, and including a first conductor connected to said main surface and a second conductor electrically connected to said first conductor; and a crystallization suppress portion between said first and second conductors for suppressing crystallization of said second conductor; wherein said first conductor includes a plug portion connected to said main surface and a bottom wall portion formed on said plug portion, and wherein said second conductor is a vertical wall portion connected to a side surface of said bottom wall portion with said crystallization suppress portion therebetween.
Claim 9
Dependent Claim
27 words
The semiconductor memory device according to claim 1, wherein said first conductor includes a horizontal bottom wall portion and said second conductor includes a vertical wall portion.
References Cited (Backward Citations)
JPH03263370A
Cited
US5290729A
Cited
US5366917A
Cited
US5623243A
Cited
US5843829A
Cited
US5597760A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |