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US6085277A
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Interrupt and message batching apparatus and method
Assignee: International Business Machines Corp
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Filing: 1997-10-15
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Granted: 2000-07-04
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Expires: 2017-10-15
Abstract
Abstract An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.
Inventors
- 👤 Gregory Michael Nordstrom
- 👤 Shawn Michael Lambeth
- 👤 Paul Edward Movall
- 👤 Daniel Frank Moertl
- 👤 Charles Scott Graham
- 👤 William Joseph Armstrong
- 👤 Thomas Rembert Sand
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F9/546
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
159 words
A system for handling I/O messages transmitted over an I/O bus, comprising: a processor complex connected to the I/O bus, said processor complex including a memory device having a message queue structure; an I/O adapter connected to the I/O bus, said I/O adapter including a message processor to process messages, to generate messages, and to send messages to the message queue structure; a signalling timer timing an interval beginning with placing a message in the message queue structure; and decision logic deciding when to signal an interrupt to said processor complex; said decision logic programs the signalling timer with a fast signal time value if the message has a relatively short latency period or with a slow signal time value if the message has a relatively long latency period, and the decision logic starts the signalling timer when the message is enqueued, and said decision logic signalling an interrupt to said processor complex when the signalling timer has elapsed.
Claim 2
Independent Claim
159 words
A system for handling I/O messages transmitted over an I/O bus, comprising: a processor complex connected to the I/O bus, said processor complex including a memory device having a message queue structure; an I/O adapter connected to the I/O bus, said I/O adapter including a message processor to process messages, to generate messages, and to send messages to the message queue structure; a signalling timer timing an interval beginning with placing a message in the message queue structure; and decision logic deciding when to signal an interrupt to said processor complex; said decision logic programs the signalling timer with a fast signal time value if the message has a relatively short latency period or with a slow signal time value if the message has a relatively long latency period, and the decision logic starts the signalling timer when the message is enqueued, and said decision logic signalling an interrupt to said processor complex when the signalling timer has elapsed.
Claim 3
Dependent Claim
67 words
The system of claim 1, wherein a message counter counting a number of messages in the message queue structure; said decision logic updating a message count in said message counter when the message is enqueued, and the decision logic signals an interrupt to the processor complex when the message count stored by the message counter exceeds the message pacing count or when the signalling timer has elapsed.
Claim 4
Dependent Claim
60 words
The system of claim 2, wherein the message is a response message from the I/O adapter to the processor complex and the message queue structure is a response message queue structure and the message count is a response message count and the message counter is a response message counter and the message pacing count is a response message pacing count.
Claim 5
Dependent Claim
74 words
The system of claim 2, wherein the message is a command message from the processor complex to the I/O adapter to command an I/O device connected to the I/O adapter to perform a function and the message queue structure is a command message queue structure and the message count is a command message count and the message counter is a command message counter and the message pacing count is a command message pacing count.
Claim 6
Dependent Claim
29 words
The system of claim 2, wherein the message pacing count is a number less than a maximum number of messages capable of being stored in the message queue structure.
Claim 7
Dependent Claim
80 words
The system of claim 2, wherein the decision logic compares the message count stored by the message counter against a maximum number of messages capable of being stored in the message queue structure, the decision logic signals an interrupt to the processor complex when the message count stored by the message counter exceeds either the message pacing count or the maximum number of messages capable of being stored in the message queue structure or when the signalling timer has elapsed.
Claim 8
Dependent Claim
47 words
The system of claim 2, wherein the processor complex initializes the I/O device with either the fast or slow signal time value, and the decision logic utilizes the fast or slow signal time value to program the signalling timer with the fast or slow signal time value.
Claim 9
Dependent Claim
47 words
The system of claim 2, wherein the processor complex implicitly includes either a fast or slow signal time value in the message based on message information contained in the message, and the decision logic utilizes the fast or slow signal time value to program the signalling timer.
Claim 10
Dependent Claim
42 words
The system of claim 2, wherein the processor complex explicitly includes either a fast or slow signal time value in the message, and the decision logic utilizes the fast or slow signal time value in the message to program the signalling timer.
Claim 11
Dependent Claim
25 words
The system of claim 2, wherein the decision logic signals an interrupt signal to the processor complex if an interrupt signal is not already active.
Claim 12
Dependent Claim
27 words
The system of claim 2, wherein the decision logic programs the signalling timer with the slow signal time value if the signalling timer is not already running.
Claim 13
Dependent Claim
33 words
The system of claim 2, wherein the decision logic programs the signalling timer with the fast signal time value if a remaining time in the signalling timer exceeds the fast response time value.
Claim 14
Dependent Claim
96 words
The system of claim 2, wherein the first message counter includes: a first pointer pointing to the last message enqueued by the message processor in the message queue structure, a second pointer pointing to the next message in the message queue structure to be processed by the processor complex, and the processor complex updates the second pointer when a message has been processed by the processor complex, and the message processor updates the first pointer upon enqueing message in the message queue structure, wherein the message count is the difference between the first and second pointers.
Claim 15
Dependent Claim
110 words
In a computer system having a first and second device interconnected by a bus, an interrupt decision sequence, comprising: sending a message from the first device to the second device, enqueing a message in a message queue located in the second device, programming a signalling timer with a fast signal time value if the first device has a relatively short latency period or with a slow signal time value if the first device has a relatively long latency period, starting the signalling timer with the programmed response time value after completion of said enqueing step, and signalling an interrupt to the second device when the the signalling timer has elapsed.
Claim 16
Dependent Claim
110 words
In a computer system having a first and second device interconnected by a bus, an interrupt decision sequence, comprising: sending a message from the first device to the second device, enqueing a message in a message queue located in the second device, programming a signalling timer with a fast signal time value if the first device has a relatively short latency period or with a slow signal time value if the first device has a relatively long latency period, starting the signalling timer with the programmed response time value after completion of said enqueing step, and signalling an interrupt to the second device when the the signalling timer has elapsed.
Claim 17
Dependent Claim
51 words
The interrupt decision sequence of claim 14, further comprising: updating a message count counting a number of messages in the message queue after completion of said enqueing step, and said signalling step signalling an interrupt when the message count exceeds the message pacing count or when the signaling timer has elapsed.
Claim 18
Dependent Claim
64 words
The interrupt decision sequence of claim 15, further comprising: comparing the message count against a maximum number of messages capable of being stored in the message queue, said signalling step signalling an interrupt when the message count exceeds the message pacing count or the maximum number of first messages capable of being stored in the message queue or when the signalling timer has elapsed.
Claim 19
Dependent Claim
45 words
The interrupt decision sequence of claim 15, said sending a message step including: implicitly including a fast or slow signal time value in the message, said programming step utilizing the fast or slow signal time value in the first message to program the signalling timer.
Claim 20
Dependent Claim
45 words
The interrupt decision sequence of claim 15, said sending a message step including: explicitly including a fast or slow signal time value in the message, said programming step utilizing the fast or slow signal time value in the first message to program the signalling timer.
Claim 21
Dependent Claim
38 words
The interrupt decision sequence of claim 15, further comprising: initializing the first device with either a fast or slow signal time value, said programming step utilizing the fast or slow signal time value to program the signalling timer.
Claim 22
Dependent Claim
104 words
The interrupt decision sequence of claim 14, further comprising: addressing the message queue with a first and second pointer wherein the first pointer points to the last message enqueued by said enqueing step and the second pointer points to a next message in the message queue to be processed by the second device, updating the second pointer when the second device processes a message in the message queue, updating the first pointer upon enqueing message in said enqueing step, and said updating a message count step including the substep of calculating the message count by finding the difference between the first and second pointers.
Claim 23
Dependent Claim
28 words
The interrupt decision sequence of claim 15, said programming step programming the signalling timer with the slow signal time value if the signalling timer is not already running.
Claim 24
Dependent Claim
34 words
The interrupt decision sequence of claim 15, said programming step programming the signalling timer with the fast signal time value if a remaining time in the signalling timer exceeds the fast signal time value.
Claim 25
Dependent Claim
30 words
The interrupt decision sequence of claim 14, wherein the message pacing count is a number less than a maximum number of messages capable of being stored in the message queue.
Claim 26
Dependent Claim
20 words
The interrupt decision sequence of claim 14, said signalling step signalling an interrupt if an interrupt is not already active.
Claim 27
Dependent Claim
58 words
The interrupt decision sequence of claim 14, wherein the first device is an I/O adapter having an I/O device connected thereto, wherein the second device is a processor complex connected to the I/O adapter via an I/O bus, wherein the message is from the I/O adapter to the processor complex and the queue is a response message queue.
Claim 28
Dependent Claim
58 words
The interrupt decision sequence of claim 14, wherein the second device is an I/O adapter having an I/O device connected thereto, wherein the first device is a processor complex connected to the I/O adapter via an I/O bus, and wherein the message is from the processor complex to the I/O adapter and queue is a command message queue.
Claim 29
Independent Claim
99 words
A method of managing a first message queue in a computer system: providing the first message queue in a memory of the computer system, generating a first message, enqueing the first message in the first message queue of the memory, programming a signalling timer with a fast signal time value if the first message has a relatively short latency period or with a slow signal time value if the first message has a relatively long latency period in response to said enqueing step enqueing the first message, and signalling a processor complex interrupt when the signalling timer has elapsed.
Claim 30
Independent Claim
99 words
A method of managing a first message queue in a computer system: providing the first message queue in a memory of the computer system, generating a first message, enqueing the first message in the first message queue of the memory, programming a signalling timer with a fast signal time value if the first message has a relatively short latency period or with a slow signal time value if the first message has a relatively long latency period in response to said enqueing step enqueing the first message, and signalling a processor complex interrupt when the signalling timer has elapsed.
Claim 31
Dependent Claim
21 words
The method of claim 27, said signalling step signalling a processor interrupt signal if a processor interrupt is not already active.
Claim 32
Dependent Claim
39 words
The method of claim 27, further comprising: updating a first message count, and said signalling step signalling a processor complex interrupt when the first message count exceeds the first message pacing count or when the signalling timer has elapsed.
Claim 33
Dependent Claim
86 words
The method of claim 29, further comprising: sending a second message, wherein the first message is from an I/O adapter to a processor complex and the second message is from the processor complex to the I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function and the first message queue is a response message queue and the first message count is a response message count and the first message pacing count is a response message pacing count.
Claim 34
Dependent Claim
69 words
The method of claim 29 further comprising: sending a second message, wherein the first message is from a processor complex to an I/O adapter and the second message is from the I/O adapter to the processor complex and the first message queue is a command message queue and the first message count is a command message count and the first message pacing count is a command message pacing count.
Claim 35
Dependent Claim
32 words
The method of claim 29, wherein a first response message pacing count is a number less than a maximum number of first messages capable of being stored in the first message queue.
Claim 36
Dependent Claim
71 words
The method of claim 29, further comprising: comparing the first message count against a maximum number of first messages capable of being stored in the first message queue, said signalling step signalling a processor complex interrupt when the first message count exceeds either the first message pacing count or the maximum number of first messages capable of being stored in the first message queue or when the signalling timer has elapsed.
Claim 37
Dependent Claim
36 words
The method of claim 29, further comprising: initializing an I/O adapter with either a fast or slow signal time value, said programming step utilizing the fast or slow first signal value to program the signalling timer.
Claim 38
Dependent Claim
52 words
The method of claim 27, said step of sending a second message implicitly includes either a fast or slow signal time value in the second message based on message information in the second message, and said programming step utilizes the fast or slow signal time value to and program the signalling timer.
Claim 39
Dependent Claim
46 words
The method of claim 29, said sending a second message step explicitly including either a fast or slow signal time value in the second message, and said programming step utilizing the fast or slow signal time value in the second message to program the signalling timer.
Claim 40
Dependent Claim
26 words
The method of claim 29, said programming step programming the signalling timer with the slow signal time value if the signalling timer is not already running.
Claim 41
Dependent Claim
32 words
The method of claim 29, said programming step programming the signalling timer with the fast signal time value if a remaining time in the signalling timer exceeds the fast signal time value.
Claim 42
Dependent Claim
111 words
The method of claim 29, further comprising: addressing the first message queue with a first and second pointer wherein the first pointer points to a next first message in the response queue to be processed by the processor complex and the second pointer points to the last first message enqueued by said enqueing step updating the first pointer when the processor complex processes a first message in the first message queue, updating the second pointer upon enqueing a first message in said enqueing step, and said updating a first message count step including the substep of calculating the first message count by finding the difference between the first and second pointers.
References Cited (Backward Citations)
US4783730A
Cited
US5507032A
Cited
US5471618A
Cited
US5513368A
Cited
US5535420A
Cited
US5761427A
Cited
US5875343A
Cited
US5708814A
Cited
US5805929A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |