US6084461A
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Charge sensitive amplifier with high common mode signal rejection
Assignee: Varex Imaging Corp
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Filing: 1996-11-29
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Granted: 2000-07-04
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Expires: 2016-11-29
Abstract
Abstract A charge sensitive amplifier with high common mode signal rejection includes an NPN bipolar junction transistor (BJT) and a P-channel metal oxide semiconductor field effect transistor (MOSFET) connected in a totem pole circuit configuration. The BJT base terminal receives a dc reference voltage, the MOSFET gate terminal receives the incoming data signal, the MOSFET drain terminal is grounded and the BJT collector terminal provides the output voltage signal and is biased by the power supply through a resistive circuit element. The MOSFET operates as a source follower amplifier with the transconductance of the BJT serving as the load at the source terminal, while the BJT operates as a common emitter amplifier with the transconductance of the MOSFET providing emitter degeneration. The signal gains of such source follower and common emitter amplifiers are substantially equal and of opposite polarities. Therefore, any common mode signal components due to common mode input signals present at the input terminals (i.e., the BJT base and MOSFET gate terminals) which would otherwise appear within the output signal are substantially cancelled, thereby resulting in a high degree of common mode signal rejection.
Inventors
- 👤 Richard E. Colbeth
- 👤 Max J. Allen
- 👤 Martin Mallinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:54
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F1/00; H03F1/08; H03F1/22; H03F1/223; H03F3/34; H03F3/343; H03F3/345
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
265 words
An apparatus including a charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a current controlled transistor circuit configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a voltage controlled transistor circuit, coupled to said current controlled transistor circuit, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and an output circuit, coupled to one or both of said current and voltage controlled transistor circuits, configured to receive and combine said data signal component and said first and second common mode signal components and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said current and voltage controlled transistor circuits are coupled together in a totem pole circuit configuration.
Claim 2
Independent Claim
265 words
An apparatus including a charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a current controlled transistor circuit configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a voltage controlled transistor circuit, coupled to said current controlled transistor circuit, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and an output circuit, coupled to one or both of said current and voltage controlled transistor circuits, configured to receive and combine said data signal component and said first and second common mode signal components and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said current and voltage controlled transistor circuits are coupled together in a totem pole circuit configuration.
Claim 3
Dependent Claim
75 words
The apparatus of claim 1, wherein said current controlled transistor circuit includes a first semiconductor output region of a first conductivity type from which said first common mode signal component is provided, said voltage controlled transistor circuit includes a second semiconductor output region of a second conductivity type from which said data signal component and said second common mode signal component are provided, and said first and second conductivity types are of opposite conductivity types.
Claim 4
Dependent Claim
32 words
The apparatus of claim 2, wherein said current controlled transistor circuit comprises an NPN bipolar junction transistor and said voltage controlled transistor circuit comprises a P-channel metal oxide semiconductor field effect transistor.
Claim 5
Dependent Claim
32 words
The apparatus of claim 2, wherein said current controlled transistor circuit comprises a PNP bipolar junction transistor and said voltage controlled transistor circuit comprises an N-channel metal oxide semiconductor field effect transistor.
Claim 6
Independent Claim
290 words
An apparatus including a charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a current controlled transistor circuit configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a voltage controlled transistor circuit, coupled to said current controlled transistor circuit, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and an output circuit, coupled to one or both of said current and voltage controlled transistor circuits, configured to receive and combine said data signal component and said first and second common mode signal components and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said current and voltage controlled transistor circuits are coupled together in an opposing circuit configuration and said output signal comprises a differential output signal with first and second opposing signal phases provided by said current and voltage controlled transistor circuits, respectively.
Claim 7
Independent Claim
290 words
An apparatus including a charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a current controlled transistor circuit configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a voltage controlled transistor circuit, coupled to said current controlled transistor circuit, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and an output circuit, coupled to one or both of said current and voltage controlled transistor circuits, configured to receive and combine said data signal component and said first and second common mode signal components and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said current and voltage controlled transistor circuits are coupled together in an opposing circuit configuration and said output signal comprises a differential output signal with first and second opposing signal phases provided by said current and voltage controlled transistor circuits, respectively.
Claim 8
Dependent Claim
62 words
The apparatus of claim 5, wherein said current controlled transistor circuit includes a first semiconductor output region of a conductivity type from which said first common mode signal component is provided and said voltage controlled transistor circuit includes a second semiconductor output region of said conductivity type from which said data signal component and said second common mode signal component are provided.
Claim 9
Dependent Claim
32 words
The apparatus of claim 6, wherein said current controlled transistor circuit comprises a PNP bipolar junction transistor and said voltage controlled transistor circuit comprises a P-channel metal oxide semiconductor field effect transistor.
Claim 10
Dependent Claim
32 words
The apparatus of claim 6, wherein said current controlled transistor circuit comprises an NPN bipolar junction transistor and said voltage controlled transistor circuit comprises an N-channel metal oxide semiconductor field effect transistor.
Claim 11
Dependent Claim
22 words
The apparatus of claim 5, wherein said output circuit comprises a plurality of circuit elements exhibiting a plurality of circuit resistance characteristics.
Claim 12
Independent Claim
267 words
An apparatus including a bipolar and metal oxide semiconductor charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a bipolar junction transistor (BJT) configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a metal oxide semiconductor field effect transistor (MOSFET), coupled to said BJT, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and a resistive output circuit, coupled to one or both of said BJT and said MOSFET, configured to receive and combine said first and second common mode signal components and said data signal component and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said BJT and said MOSFET are coupled together in a totem pole circuit configuration.
Claim 13
Independent Claim
267 words
An apparatus including a bipolar and metal oxide semiconductor charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a bipolar junction transistor (BJT) configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a metal oxide semiconductor field effect transistor (MOSFET), coupled to said BJT, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and a resistive output circuit, coupled to one or both of said BJT and said MOSFET, configured to receive and combine said first and second common mode signal components and said data signal component and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said BJT and said MOSFET are coupled together in a totem pole circuit configuration.
Claim 14
Dependent Claim
69 words
The apparatus of claim 10, wherein said BJT includes a first semiconductor output region of a first conductivity type from which said first common mode signal component is provided, said MOSFET includes a second semiconductor output region of a second conductivity type from which said data signal component and said second common mode signal component are provided, and said first and second conductivity types are of opposite conductivity types.
Claim 15
Dependent Claim
19 words
The apparatus of claim 11, wherein said BJT comprises an NPN BJT and said MOSFET comprises a P-channel MOSFET.
Claim 16
Dependent Claim
19 words
The apparatus of claim 12, wherein said BJT comprises a PNP BJT and said MOSFET comprises an N-channel MOSFET.
Claim 17
Independent Claim
289 words
An apparatus including a bipolar and metal oxide semiconductor charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a bipolar junction transistor (BJT) configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a metal oxide semiconductor field effect transistor (MOSFET), coupled to said BJT, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and a resistive output circuit, coupled to one or both of said BJT and said MOSFET, configured to receive and combine said first and second common mode signal components and said data signal component and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said BJT and said MOSFET are coupled together in an opposing circuit configuration and said output signal comprises a differential output signal with first and second opposing signal phases provided by said BJT and MOSFET, respectively.
Claim 18
Independent Claim
289 words
An apparatus including a bipolar and metal oxide semiconductor charge sensitive amplifier with high common mode signal rejection, said charge sensitive amplifier comprising: a bipolar junction transistor (BJT) configured to receive a dc input reference with a common mode input signal and in accordance therewith provide a first common mode signal component, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; a metal oxide semiconductor field effect transistor (MOSFET), coupled to said BJT, configured to receive a data input signal with said common mode input signal and in accordance therewith provide a data signal component and a second common mode signal component, wherein a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and a resistive output circuit, coupled to one or both of said BJT and said MOSFET, configured to receive and combine said first and second common mode signal components and said data signal component and in accordance therewith provide an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said BJT and said MOSFET are coupled together in an opposing circuit configuration and said output signal comprises a differential output signal with first and second opposing signal phases provided by said BJT and MOSFET, respectively.
Claim 19
Dependent Claim
56 words
The apparatus of claim 14, wherein said BJT includes a first semiconductor output region of a conductivity type from which said first common mode signal component is provided and said MOSFET includes a second semiconductor output region of said conductivity type from which said data signal component and said second common mode signal component are provided.
Claim 20
Dependent Claim
19 words
The apparatus of claim 15, wherein said BJT comprises a PNP BJT and said MOSFET comprises a P-channel MOSFET.
Claim 21
Dependent Claim
19 words
The apparatus of claim 15, wherein said BJT comprises an NPN BJT and said MOSFET comprises an N-channel MOSFET.
Claim 22
Independent Claim
238 words
A method of amplifying a charge sensitive signal with high common mode signal rejection, said method comprising the steps of: receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit, wherein said current and voltage controlled transistor circuits are coupled together in a totem pole circuit configuration and a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and combining said first and second common mode signal components and said data signal component and in accordance therewith generating an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain: wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; and wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another.
Claim 23
Independent Claim
238 words
A method of amplifying a charge sensitive signal with high common mode signal rejection, said method comprising the steps of: receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit, wherein said current and voltage controlled transistor circuits are coupled together in a totem pole circuit configuration and a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and combining said first and second common mode signal components and said data signal component and in accordance therewith generating an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain: wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; and wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another.
Claim 24
Dependent Claim
195 words
The method of claim 18, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with said current controlled transistor circuit including a first semiconductor output region of a first conductivity type from which said first common mode signal component is provided; said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with said voltage controlled transistor circuit including a second semiconductor output region of a second conductivity type from which said data signal component and said second common mode signal component are provided; and said first and second conductivity types are of opposite conductivity types.
Claim 25
Dependent Claim
140 words
The method of claim 19, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with an NPN bipolar junction transistor; and said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with a P-channel metal oxide semiconductor field effect transistor.
Claim 26
Dependent Claim
140 words
The method of claim 19, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with a PNP bipolar junction transistor; and said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with an N-channel metal oxide semiconductor field effect transistor.
Claim 27
Independent Claim
263 words
A method of amplifying a charge sensitive signal with high common mode signal rejection, said method comprising the steps of: receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit, wherein said current and voltage controlled transistor circuits are coupled together in an opposing circuit configuration and a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and combining said first and second common mode signal components and said data signal component and in accordance therewith generating an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said output signal comprises a differential output signal with first and second opposing signal phases provided by said current and voltage controlled transistor circuits, respectively.
Claim 28
Independent Claim
263 words
A method of amplifying a charge sensitive signal with high common mode signal rejection, said method comprising the steps of: receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit, wherein a ratio of said first common mode signal component to said common mode input signal equals a first signal gain; receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit, wherein said current and voltage controlled transistor circuits are coupled together in an opposing circuit configuration and a ratio of said second common mode signal component to said common mode input signal equals a second signal gain; and combining said first and second common mode signal components and said data signal component and in accordance therewith generating an output signal which corresponds to said data input signal, wherein a ratio of said output signal to said data input signal substantially equals said second signal gain; wherein said data input signal is single-ended and said dc input reference and said data input signal are unrelated to one another; wherein said first and second signal gains are substantially equal and of opposite polarities and said first and second common mode signal components substantially cancel one another; and wherein said output signal comprises a differential output signal with first and second opposing signal phases provided by said current and voltage controlled transistor circuits, respectively.
Claim 29
Dependent Claim
182 words
The method of claim 22, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with said current controlled transistor circuit including a first semiconductor output region of a conductivity type from which said first common mode signal component is provided; and said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with said voltage controlled transistor circuit including a second semiconductor output region of said conductivity type from which said data signal component and said second common mode signal component are provided.
Claim 30
Dependent Claim
140 words
The method of claim 23, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with a PNP bipolar junction transistor; and said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with a P-channel metal oxide semiconductor field effect transistor.
Claim 31
Dependent Claim
140 words
The method of claim 23, wherein: said step of receiving a dc input reference with a common mode input signal and in accordance therewith generating a first common mode signal component with a current controlled transistor circuit comprises receiving said dc input reference with said common mode input signal and in accordance therewith generating said first common mode signal component with an NPN bipolar junction transistor; and said step of receiving a data input signal with said common mode input signal and in accordance therewith generating a data signal component and a second common mode signal component with a voltage controlled transistor circuit comprises receiving said data input signal with said common mode input signal and in accordance therewith generating said data signal component and said second common mode signal component with an N-channel metal oxide semiconductor field effect transistor.
Claim 32
Dependent Claim
81 words
The method of claim 2, wherein said step of combining said first and second common mode signal components and said data signal component and in accordance therewith generating an output signal which corresponds to said data input signal comprises combining said first and second common mode signal components and said data signal component and in accordance therewith generating said output signal which corresponds to said data input signal with a plurality of circuit elements exhibiting a plurality of circuit resistance characteristics.
References Cited (Backward Citations)
US4220873A
Cited
US4216435A
Cited
US4366522A
Cited
EP0159654A2
Cited
US4596958A
Cited
US4746814A
Cited
US4740722A
Cited
US5576646A
Cited
US5689197A
Cited
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