BIMOS-type current switch apparatus

Claim 2

A current switch apparatus comprising: a logic signal input terminal; an output terminal; a power supply terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a MOS transistor, connected between said power supply voltage terminal and the emitter of said bipolar transistor and having a gate connected to said logic signal input terminal; and a constant current source connected to the emitter of said bipolar transistor, wherein said MOS transistor is of an N-channel type.

Claim 3

An apparatus as set forth in claim 1, wherein when a voltage at said logic signal input terminal is at a first level, said MOS transistor is turned ON so that said bipolar transistor is turned OFF, and wherein when the voltage at said logic signal input terminal is at a second level, said MOS transistor is turned OFF so that said bipolar transistor is turned ON.

Claim 4

A current switch apparatus comprising: a logic signal input terminal; an output terminal; a power supply terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said power supply terminal, a base connected to said reference voltage terminal, and an emitter; a MOS transistor, connected between said output terminal and the emitter of said bipolar transistor and having a gate connected to said logic signal input terminal; and a constant current source connected to the emitter of said bipolar transistor, wherein said MOS transistor is of an N-channel type.

Claim 5

A current switch apparatus comprising: a logic signal input terminal; an output terminal; a power supply terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said power supply terminal, a base connected to said reference voltage terminal, and an emitter; a MOS transistor, connected between said output terminal and the emitter of said bipolar transistor and having a gate connected to said logic signal input terminal; and a constant current source connected to the emitter of said bipolar transistor, wherein said MOS transistor is of an N-channel type.

Claim 6

An apparatus as set forth in claim 3, wherein when a voltage at said logic signal input terminal is at a first level, said MOS transistor is turned ON so that said bipolar transistor is turned OFF, and wherein when the voltage at said logic signal input terminal is at a second level, said MOS transistor is turned OFF so that said bipolar transistor is turned ON.

Claim 7

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply terminal; a reference voltage terminal; a plurality of bipolar transistors, each having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, each being connected between said power supply terminal and the emitter of one of said bipolar transistors and having a gate connected to one of said logic signal input terminals; and a plurality of constant current sources each connected to the emitter of one of said bipolar transistors.

Claim 8

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply terminal; a reference voltage terminal; a plurality of bipolar transistors, each having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, each being connected between said power supply terminal and the emitter of one of said bipolar transistors and having a gate connected to one of said logic signal input terminals; and a plurality of constant current sources each connected to the emitter of one of said bipolar transistors.

Claim 9

An apparatus a set forth in claim 5, wherein said MOS transistors are of an N-channel type.

Claim 10

An apparatus as set forth in claim 5, wherein said MOS transistors are of a P-channel type.

Claim 11

An apparatus as set forth in claim 5, wherein when a voltage at one of said logic signal input terminals is at a first level, a respective one of said MOS transistors is turned ON so that a respective one of said bipolar transistors is turned OFF, and wherein when the voltage at one of said logic signal input terminals is at a second level, a respective one of said MOS transistors is turned OFF so that a respective one of said bipolar transistors is turned ON.

Claim 12

An apparatus as set forth in claim 5, wherein said constant current sources have the same current flowing therethrough.

Claim 13

An apparatus as set forth in claim 5, wherein a ratio of currents flowing through said constant current sources is 1:2:2 2 . . . .

Claim 14

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply terminal; a reference voltage terminal; a plurality of bipolar transistors, each having a collector connected to said power supply terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, each being connected between said output terminal and the emitter of one of said bipolar transistors and having a gate connected to one of said logic signal input terminals; and a plurality of constant current sources each connected to the emitter of one of said bipolar transistors.

Claim 15

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply terminal; a reference voltage terminal; a plurality of bipolar transistors, each having a collector connected to said power supply terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, each being connected between said output terminal and the emitter of one of said bipolar transistors and having a gate connected to one of said logic signal input terminals; and a plurality of constant current sources each connected to the emitter of one of said bipolar transistors.

Claim 16

An apparatus as set forth in claim 11, wherein said MOS transistors are of an N-channel type.

Claim 17

An apparatus as set forth in claim 11, wherein said MOS transistors are of a P-channel type.

Claim 18

An apparatus as set forth in claim 11, wherein when voltage at one of said logic signal input terminals is at a first level, a respective one of said MOS transistors is turned ON so that a respective one of said bipolar transistors is turned OFF, and wherein when the voltage at one of said logic signal input terminals is at a second level, a respective one of said MOS transistors is turned OFF so that a respective one of said bipolar transistors is turned ON.

Claim 19

An apparatus as set forth in claim 11, wherein said constant current sources have the same current flowing therethrough.

Claim 20

An apparatus as set forth in claim 11, wherein a ratio of currents flowing through said constant current sources is 1:2:2 2 . . . .

Claim 21

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply voltage terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, being connected between said power supply terminal and the emitter of said bipolar transistor and having a gate connected to one of said logic signal input terminals; and a constant current source connected to the emitter of said bipolar transistor.

Claim 22

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply voltage terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, being connected between said power supply terminal and the emitter of said bipolar transistor and having a gate connected to one of said logic signal input terminals; and a constant current source connected to the emitter of said bipolar transistor.

Claim 23

An apparatus as set forth in claim 17, wherein said MOS transistors are of an N-channel type.

Claim 24

An apparatus as set forth in claim 17, wherein said MOS transistors are of a P-channel type.

Claim 25

An apparatus as set forth in claim 17, wherein when a voltage at one of said logic signal input terminals is at a first level, a respective one of said MOS transistors is turned ON so that said bipolar transistor is turned OFF, and wherein when voltages at all of said logic signal input terminals are at a second level, all of said MOS transistors are turned OFF so that said bipolar transistor is turned ON.

Claim 26

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply voltage terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, being connected between said output terminal and the emitter of said bipolar transistor and having a gate connected to one of said logic signal input terminals; and a constant current source connected to the emitter of said bipolar transistor.

Claim 27

A current switch apparatus comprising: a plurality of logic signal input terminals; an output terminal; a power supply voltage terminal; a reference voltage terminal; a bipolar transistor having a collector connected to said output terminal, a base connected to said reference voltage terminal, and an emitter; a plurality of MOS transistors, being connected between said output terminal and the emitter of said bipolar transistor and having a gate connected to one of said logic signal input terminals; and a constant current source connected to the emitter of said bipolar transistor.

Claim 28

An apparatus as set forth in claim 21, wherein said MOS transistors are of an N-channel type.

Claim 29

An apparatus as set forth in claim 21, wherein said MOS transistors are of a P-channel type.

Claim 30

An apparatus as set forth in claim 21, wherein when a voltage at one of said logic signal input terminals is at a first level, a respective one of said MOS transistors is turned ON so that said bipolar transistor is turned OFF, and wherein when voltages at all of said logic signal input terminals are at a second level, all of said MOS transistors are turned OFF so that said bipolar transistor is turned ON.

Claim 31

A current switch apparatus comprising: plurality of logic signal input terminals; an output terminal a power supply terminal; a reference voltage terminal; a column of bipolar transistors, having collectors connected to said output terminal bases connected to said reference voltage terminal and emitters; a column of constant current sources each connected to one of the emitters of said bipolar transistors; a plurality of first conductive line each connected to one of said constant current sources; and a plurality of rows of MOS transistors, each row of said MOS transistors being connected between said power supply terminal and one of said conductive line, gates of each column of said MOS transistors being connected to one of said logic signal terminals.

Claim 32

A current switch apparatus comprising: plurality of logic signal input terminals; an output terminal a power supply terminal; a reference voltage terminal; a column of bipolar transistors, having collectors connected to said output terminal bases connected to said reference voltage terminal and emitters; a column of constant current sources each connected to one of the emitters of said bipolar transistors; a plurality of first conductive line each connected to one of said constant current sources; and a plurality of rows of MOS transistors, each row of said MOS transistors being connected between said power supply terminal and one of said conductive line, gates of each column of said MOS transistors being connected to one of said logic signal terminals.

Claim 33

An apparatus as set forth in claim 25, wherein a certain number of said MOS transistors are always turned OFF regardless of a voltage applied to respective logic signal input terminals.

Claim 34

An apparatus as set forth in claim 25, further comprising a semiconductor substrate means divided into a bipolar transistor area and a MOS transistor area.

Claim 35

An apparatus as set forth in claim 27, further comprising: a common collector region of said bipolar transistors formed within said semiconductor substrate means in said bipolar transistor area; a common base region of said bipolar transistors formed within said common collector region; and a plurality of emitter regions each for one of said bipolar transistors, formed within said common base region.

Claim 36

An apparatus as set forth in claim 27, further comprising: a plurality of first impurity regions formed within said semiconductor substrate means in said MOS transistor area, each of said first impurity regions being for one group of a group of sources and a group of drains of said MOS transistors; a plurality of columns of second impurity regions formed within said semiconductor substrate means in said MOS transistor area, each column being for the other group of the group of sources and the group of drains of said MOS transistors.

Claim 37

An apparatus as set forth in claim 29, wherein said columns of second impurity regions are provided for every two columns of said MOS transistors.

Claim 38

An apparatus as set forth in claim 29, wherein said first conductive line are selectively connected to said first impurity regions via contact holes.

Claim 39

An apparatus as set forth in claim 27, further comprising: a plurality of second conductive line each connected to one of said logic signal input terminals, said second conductive line serving as gates of said MOS transistors; an insulating layer formed between said semiconductor substrate in said MOS transistor area and said second conductive line, said insulating layer being thicker in a certain number of said MOS transistors than in the other of said MOS transistors.

Claim 40

An apparatus as set forth in claim 27, further comprising: a plurality of second conductive lines each connected to one of said logic signal input terminals, said second conductive lines respectively serving as gates of said MOS transistors; an insulating layer formed between said semiconductor substrate in said MOS transistor area and said second conductive lines, a density of impurities on surfaces of said semiconductor substrate beneath said insulating layer being larger in a certain number of said MOS transistors than in the other of said MOS transistors.