US6083842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication of a via plug having high aspect ratio with a diffusion barrier layer effectively surrounding the via plug
Assignee: GlobalFoundries Inc
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Filing: 1999-02-19
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Granted: 2000-07-04
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Expires: 2019-02-19
Abstract
Abstract A method for efficiently fabricating a via plug having high aspect ratio within an insulating layer with a diffusion barrier layer effectively surrounding the via plug. The method includes the steps of depositing a via photoresist layer over a first metal line of a first conductive material and etching a via hole in the via photoresist layer. The first conductive material of the first metal line is exposed at a bottom wall of the via hole. A via plug of a second conductive material is deposited into the via hole, and the via plug makes a conductive path with the first metal line. The via photoresist layer is then removed such that any side wall of the via plug is exposed. A first diffusion barrier layer is then deposited onto any exposed surface of the second conductive material of the via plug. A via insulating layer is then spin-coated to surround the via plug and a trench insulating layer is also deposited over the via insulating layer. A trench is then etched over the via plug having the first diffusion barrier layer, and the via plug with the first diffusion barrier layer is exposed as part of a bottom wall of the trench. A second diffusion barrier layer is then deposited onto the walls of the trench, and a third conductive material is deposited into the trench to form a second metal line. The second metal line makes a conductive path with the second conductive material of the via plug. Thus, the present invention avoids the prior art method of depositing a diffusion barrier layer into the via hole within a via insulating layer before filling the via hole with the via plug. With the present invention, a via plug with high aspect ratio may be efficiently formed with the diffusion barrier layer effectively surrounding the via plug.
Inventors
- 👤 Robin Cheung
- 👤 Sergey Lopatin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:27
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/038; H10W20/039; H10W20/033; H10W20/063
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
129 words
A method for fabricating a via plug within an integrated circuit wafer, the method comprising the steps of: A. depositing a via photoresist layer over a first metal line of a first conductive material; B. etching a via hole in said via photoresist layer, wherein said first conductive material of said first metal line is exposed at a bottom wall of said via hole; C. depositing a via plug of a second conductive material into said via hole, wherein said via plug is conductively coupled to said first metal line; D. removing said via photoresist layer such that any side wall of said via plug is exposed; and E. selectively depositing a first diffusion barrier layer onto any exposed surface of said second conductive material of said via plug.
Claim 2
Independent Claim
129 words
A method for fabricating a via plug within an integrated circuit wafer, the method comprising the steps of: A. depositing a via photoresist layer over a first metal line of a first conductive material; B. etching a via hole in said via photoresist layer, wherein said first conductive material of said first metal line is exposed at a bottom wall of said via hole; C. depositing a via plug of a second conductive material into said via hole, wherein said via plug is conductively coupled to said first metal line; D. removing said via photoresist layer such that any side wall of said via plug is exposed; and E. selectively depositing a first diffusion barrier layer onto any exposed surface of said second conductive material of said via plug.
Claim 3
Dependent Claim
35 words
The method of claim 1, further including the step of: selectively depositing said first diffusion barrier layer onto any exposed surface of said first conductive material of said first metal line in said step E.
Claim 4
Dependent Claim
45 words
The method of claim 1, wherein said via plug is deposited into said via hole using electroless deposition with the first conductive material of said first metal line at the bottom wall of said via hole acting as an autocatalytic surface for said electroless deposition.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein said second conductive material of said via plug is copper.
Claim 6
Dependent Claim
27 words
The method of claim 4, wherein said first conductive material of said first metal line and said third conductive material of said second metal line are copper.
Claim 7
Dependent Claim
18 words
The method of claim 1, wherein said first diffusion barrier layer is comprised of cobalt tungsten phosphide (CoWP).
Claim 8
Dependent Claim
27 words
The method of claim 1, wherein said first diffusion barrier layer is selected from the group consisting of tungsten (W), tungsten nitride (WN), and tantalum nitride (TaN).
Claim 9
Dependent Claim
112 words
The method of claim 1, further including the steps of: spin coating a via insulating layer of low dielectric constant to surround said via plug; depositing a trench insulating layer over said via insulating layer; etching a trench, over said via plug having said first diffusion barrier layer, wherein said via plug with said first diffusion barrier layer is exposed as part of a bottom wall of said trench; depositing a second diffusion barrier layer onto walls of said trench; and depositing a third conductive material into said trench to form a second metal line, wherein said second metal line is conductively coupled to said second conductive material of said via plug.
Claim 10
Dependent Claim
18 words
The method of claim 8, wherein said third conductive material is deposited into said trench using electroplating deposition.
Claim 11
Dependent Claim
40 words
The method of claim 8, wherein said second diffusion barrier layer is selected from the group consisting of tantalum, tantalum nitride, tantalum copper, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium nitride, titanium/titanium nitride, and titanium silicon nitride.
Claim 12
Dependent Claim
24 words
The method of claim 8, further including the step of: polishing a top surface of said integrated circuit wafer using a chemical mechanical polish.
Claim 13
Independent Claim
313 words
A method for fabricating a via plug within an integrated circuit wafer, the method comprising the steps of: depositing a via photoresist layer over a first metal line of copper; etching a via hole in said via photoresist layer, wherein said copper of said first metal line is exposed at a bottom wall of said via hole; depositing a via plug of copper into said via hole using electroless deposition with the copper of said first metal line at the bottom wall of said via hole acting as an autocatalytic surface for said electroless deposition of copper into said via hole, wherein said via plug is conductively coupled to said first metal line; removing said via photoresist layer such that any side wall of said via plug is exposed; selectively depositing a first diffusion barrier layer of cobalt tungsten phosphide (CoWP) onto any exposed surface of copper of said via plug and onto any exposed surface of said copper of said first metal line; spin coating a via insulating layer of low dielectric constant to surround said via plug; depositing a trench insulating layer over said via insulating layer; etching a trench over said via plug having said first diffusion barrier layer, wherein said via plug with said first diffusion barrier layer is exposed as part of a bottom wall of said trench; depositing a second diffusion barrier layer onto walls of said trench, wherein said second diffusion barrier layer is selected from the group consisting of tantalum, tantalum nitride, tantalum copper, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium nitride, titanium/titanium nitride, and titanium silicon nitride; depositing copper into said trench to form a second metal line using electroplating deposition, wherein said second metal line is conductively coupled to said copper of said via plug; and polishing a top surface of said integrated circuit wafer using a chemical mechanical polish.
Claim 14
Independent Claim
313 words
A method for fabricating a via plug within an integrated circuit wafer, the method comprising the steps of: depositing a via photoresist layer over a first metal line of copper; etching a via hole in said via photoresist layer, wherein said copper of said first metal line is exposed at a bottom wall of said via hole; depositing a via plug of copper into said via hole using electroless deposition with the copper of said first metal line at the bottom wall of said via hole acting as an autocatalytic surface for said electroless deposition of copper into said via hole, wherein said via plug is conductively coupled to said first metal line; removing said via photoresist layer such that any side wall of said via plug is exposed; selectively depositing a first diffusion barrier layer of cobalt tungsten phosphide (CoWP) onto any exposed surface of copper of said via plug and onto any exposed surface of said copper of said first metal line; spin coating a via insulating layer of low dielectric constant to surround said via plug; depositing a trench insulating layer over said via insulating layer; etching a trench over said via plug having said first diffusion barrier layer, wherein said via plug with said first diffusion barrier layer is exposed as part of a bottom wall of said trench; depositing a second diffusion barrier layer onto walls of said trench, wherein said second diffusion barrier layer is selected from the group consisting of tantalum, tantalum nitride, tantalum copper, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium nitride, titanium/titanium nitride, and titanium silicon nitride; depositing copper into said trench to form a second metal line using electroplating deposition, wherein said second metal line is conductively coupled to said copper of said via plug; and polishing a top surface of said integrated circuit wafer using a chemical mechanical polish.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |