US6083829A — Use of a low resistivity Cu3 Ge interlayer as an …

Claim 1

Independent Claim 129 words

A method for forming a metal interconnect structure, on a semiconductor substrate, comprising the steps of: providing a insulator layer, on said semiconductor substrate, with openings in said insulator layer, exposing underlying conductive elements; depositing a barrier layer; depositing a germanium layer; depositing a copper layer; annealing to form a Cu 3 Ge, intermetallic layer, between a top portion of said copper layer, and said barrier layer, with the formation of said intermetallic layer consuming all of said germanium layer, and consuming a bottom portion of said copper layer; and patterning of said top portion of said copper layer, of said Cu 3 Ge intermetallic layer, and of said barrier layer, via dry etching procedures, or via a copper chemical mechanical polishing procedure, to form said metal interconnect structure.

Claim 2

Independent Claim 129 words

A method for forming a metal interconnect structure, on a semiconductor substrate, comprising the steps of: providing a insulator layer, on said semiconductor substrate, with openings in said insulator layer, exposing underlying conductive elements; depositing a barrier layer; depositing a germanium layer; depositing a copper layer; annealing to form a Cu 3 Ge, intermetallic layer, between a top portion of said copper layer, and said barrier layer, with the formation of said intermetallic layer consuming all of said germanium layer, and consuming a bottom portion of said copper layer; and patterning of said top portion of said copper layer, of said Cu 3 Ge intermetallic layer, and of said barrier layer, via dry etching procedures, or via a copper chemical mechanical polishing procedure, to form said metal interconnect structure.

Claim 3

Dependent Claim 18 words

The method of claim 1, wherein said underlying conductive elements are active device regions in said semiconductor substrate.

Claim 4

Dependent Claim 32 words

The method of claim 1, wherein said underlying conductive elements are conductive plugs, used for contact to active device regions in said semiconductor substrate, or used to contact other metal interconnect structures.

Claim 5

Dependent Claim 34 words

The method of claim 1, wherein said barrier layer is titanium nitride, deposited using CVD procedures, at a temperature between about 200 to 450° C., to a thickness between about 100 to 500 Angstroms.

Claim 6

Dependent Claim 38 words

The method of claim 1, wherein said germanium layer is deposited using CVD procedures, at a temperature between about 200 to 450° C., to a thickness between about 10 to 100 Angstroms, using GeH 4 as a source.

Claim 7

Dependent Claim 37 words

The method of claim 1, wherein said copper layer is deposited using CVD procedures, at a temperature between about 150 to 450° C., to a thickness between about 200 to 1500 Angstroms, using copper hfac-TMVS as reactants.

Claim 8

Dependent Claim 53 words

The method of claim 1, wherein said Cu 3 Ge intermetallic layer is formed via an anneal procedure, performed using rapid thermal anneal, or conventional furnace procedures, at a temperature between about 150 to 450° C., for a time between about 0.5 to 30 min, in either hydrogen, hydrogen-nitrogen, or in a vacuum.

Claim 9

Dependent Claim 35 words

The method of claim 1, wherein said Cu 3 Ge intermetallic layer is formed to a thickness between about 15 to 150 Angstroms, and with a resistivity between about 5 to 6E-6 ohm - cm.

Claim 10

Independent Claim 172 words

A method for forming a metal interconnect structure, on a semiconductor substrate, comprised of a low resistivity Cu 3 Ge intermetallic layer, located between an underlying titanium nitride barrier layer, and an overlying copper layer, comprising the steps of: providing an insulator layer, on said semiconductor substrate, with openings in said insulator layer, exposing underlying conductive elements; depositing said titanium nitride barrier layer, in a CVD tool; depositing a germanium layer, in said CVD tool; depositing said copper layer, in said CVD tool; forming said low resistivity Cu 3 Ge intermetallic layer, on said titanium nitride barrier layer, consuming said germanium layer, and consuming a bottom portion of said copper layer, via an anneal procedure, or forming said low resistivity Cu 3 Ge intermetallic layer, in situ, during deposition of said copper layer; and patterning of a top, unconsumed portion of said copper layer, of said Cu 3 Ge layer, and of said titanium nitride layer, via dry etching, or via copper chemical mechanical polishing procedures, to form said metal interconnect structure.

Claim 11

Independent Claim 172 words

A method for forming a metal interconnect structure, on a semiconductor substrate, comprised of a low resistivity Cu 3 Ge intermetallic layer, located between an underlying titanium nitride barrier layer, and an overlying copper layer, comprising the steps of: providing an insulator layer, on said semiconductor substrate, with openings in said insulator layer, exposing underlying conductive elements; depositing said titanium nitride barrier layer, in a CVD tool; depositing a germanium layer, in said CVD tool; depositing said copper layer, in said CVD tool; forming said low resistivity Cu 3 Ge intermetallic layer, on said titanium nitride barrier layer, consuming said germanium layer, and consuming a bottom portion of said copper layer, via an anneal procedure, or forming said low resistivity Cu 3 Ge intermetallic layer, in situ, during deposition of said copper layer; and patterning of a top, unconsumed portion of said copper layer, of said Cu 3 Ge layer, and of said titanium nitride layer, via dry etching, or via copper chemical mechanical polishing procedures, to form said metal interconnect structure.

Claim 12

Dependent Claim 18 words

The method of claim 9, wherein said underlying conductive elements are active device regions in said semiconductor substrate.

Claim 13

Dependent Claim 33 words

The method of claim 9, wherein said underlying conductive elements are conductive plugs, used in turn to contact active device regions in said semiconductor substrate, or used to contact other metal interconnect structures.

Claim 14

Dependent Claim 37 words

The method of claim 9, wherein said CVD tool is a cluster type tool, used to deposit said titanium nitride layer, said germanium layer, and said copper layer, in situ, without exposure to the atmosphere between depositions.

Claim 15

Dependent Claim 35 words

The method of claim 9, wherein said titanium nitride barrier layer is deposited in said CVD tool, at a temperature between about 200 to 450° C., to a thickness between about 100 to 500 Angstroms.

Claim 16

Dependent Claim 38 words

The method of claim 9, wherein said germanium layer is deposited in said CVD tool, at a temperature between about 200 to 450° C., to a thickness between about 10 to 100 Angstroms, using GeH 4 as reactants.

Claim 17

Dependent Claim 37 words

The method of claim 9, wherein said copper layer is deposited in said CVD tool, at a temperature between about 150 to 450° C., to a thickness between about 200 to 1500 Angstroms, using copper-htac-TMVS as reactants.

Claim 18

Dependent Claim 78 words

The method of claim 9, wherein said Cu 3 Ge intermetallic layer is formed using an anneal procedure, where said Cu 3 Ge intermetallic layer was not formed in situ during deposition, and was formed via the use of using either rapid thermal annealing, or conventional furnace procedures, at a temperature between about 150 to 450° C., for a time between about 0.5 to 30 min., in either a hydrogen, or in a hydrogen--nitrogen ambient, or in vacuum.

Claim 19

Dependent Claim 32 words

The method of claim 9, wherein said Cu 3 Ge intermetallic layer is formed to a thickness between about 15 to 150 Angstroms, with a resistivity between about 5 to 6E-6 ohm-cm.

Claim 20

Independent Claim 213 words

A method for forming a metal interconnect structure, on a semiconductor substrate, using a electrochemical deposited, copper layer, comprising the steps of: providing an insulator layer, on said semiconductor substrate, with opening in said insulator layer exposing underlying conductive elements; depositing a barrier layer; depositing a germanium layer; depositing a copper seed layer, with said copper seed layer not extending to a beveled edge of said semiconductor substrate, leaving said copper seed layer, on said germanium layer, only on the top surface of said semiconductor substrate; annealing to form a Cu 3 Ge intermetallic layer, with said C 3 Ge intermetallic layer created from total consumption of said germanium layer, and from consumption of a bottom portion of overlying copper seed layer, resulting in a thinned, top portion of said copper seed layer, on said Cu 3 Ge intermetallic layer, on the top surface of said semiconductor substrate; forming a thick copper layer on said thinned, top portion of said copper seed layer, on the top surface of said semiconductor substrate; and patterning, via dry etching, or via copper chemical mechanical polishing procedures, of said thick copper layer, said thinned, top portion of said copper seed layer, said Cu 3 Ge intermetallic layer, and said barrier layer, to form said metal interconnect structure.

Claim 21

Independent Claim 213 words

A method for forming a metal interconnect structure, on a semiconductor substrate, using a electrochemical deposited, copper layer, comprising the steps of: providing an insulator layer, on said semiconductor substrate, with opening in said insulator layer exposing underlying conductive elements; depositing a barrier layer; depositing a germanium layer; depositing a copper seed layer, with said copper seed layer not extending to a beveled edge of said semiconductor substrate, leaving said copper seed layer, on said germanium layer, only on the top surface of said semiconductor substrate; annealing to form a Cu 3 Ge intermetallic layer, with said C 3 Ge intermetallic layer created from total consumption of said germanium layer, and from consumption of a bottom portion of overlying copper seed layer, resulting in a thinned, top portion of said copper seed layer, on said Cu 3 Ge intermetallic layer, on the top surface of said semiconductor substrate; forming a thick copper layer on said thinned, top portion of said copper seed layer, on the top surface of said semiconductor substrate; and patterning, via dry etching, or via copper chemical mechanical polishing procedures, of said thick copper layer, said thinned, top portion of said copper seed layer, said Cu 3 Ge intermetallic layer, and said barrier layer, to form said metal interconnect structure.

Claim 22

Dependent Claim 34 words

The method of claim 18, wherein said barrier layer is titanium nitride, deposited using CVD procedures, at a temperature between about 200 to 450° C., to a thickness between about 100 to 500 Angstroms.

Claim 23

Dependent Claim 38 words

The method of claim 18, wherein said germanium layer is deposited using CVD procedures, at a temperature between about 200 to 450° C., to a thickness between about 10 to 100 Angstroms, using GeH 4 as a source.

Claim 24

Dependent Claim 37 words

The method of claim 18, wherein said copper seed layer is deposited using CVD procedures, at a temperature between about 150 to 450° C., to a thickness between about 200 to 1500 Angstroms, using copper-hfac-TMVS as reactants.

Claim 25

Dependent Claim 39 words

The method of claim 18, wherein said copper seed layer is not extended to the beveled edge of said semiconductor substrate, via use of a clamp ring, on said semiconductor substrate, during the deposition of said copper seed layer.

Claim 26

Dependent Claim 42 words

The method of claim 18, wherein said said Cu 3 Ge intermetallic layer is formed using either rapid thermal anneal, or conventional furnace procedures, at a temperature between about 150 to 450° C., to a thickness between about 15 to 150 Angstroms.

Claim 27

Dependent Claim 35 words

The method of claim 18, wherein said said Cu 3 Ge intermetallic layer is formed to a thickness between about 15 to 150 Angstroms, with a resistivity between about 5 to 6E-6 ohm - cm.

Claim 28

Dependent Claim 24 words

The method of claim 18, wherein said thinned, top portion of said copper seed layer has a thickness between about 15 to 150 Angstroms.

Claim 29

Dependent Claim 58 words

The method of claim 18, wherein said thick copper layer is formed using an electrochemical deposition procedure, to a thickness between about 3000 to 15000 Angstroms, using dissociation and reduction of copper sulfate at a temperature of about 30° C., at atmospheric pressure, with a deposition rate, for said thick copper layer, between about 2000 to 6000 Angstroms/min.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-07-04	2004-01-03	2004-07-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-07-04	2008-01-03	2008-07-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-07-04	2012-01-03	2012-07-04	$7700.00	Window Closed / Lapsed

Use of a low resistivity Cu3 Ge interlayer as an adhesion promoter between copper and tin layers

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