Method for manufacturing DRAM capacitor

Claim 1

A method for manufacturing a DRAM capacitor comprising: providing a substrate having field effect transistor formed thereon, wherein the field effect transistor includes a source region and a drain region; forming a first dielectric layer and then an inter-layer dielectric layer over the substrate; etching the inter-layer dielectric layer to form a pattern having a narrow opening; forming a second dielectric layer over the inter-layer dielectric layer; etching the second dielectric layer to form a pattern having a wide opening exposing the narrow opening, then continuing etching down through the first dielectric layer, transferring the pattern on the narrow opening to the first dielectric layer and forming a contact window that exposes a source/drain region; forming a first conductive layer over the substrate covering the wide opening and completely filling the contact window so that the conductive layer is electrically coupled to the exposed source/drain region; removing the second dielectric layer to expose the inter-layer dielectric layer and the conductive layer; forming a dielectric film layer over the exposed first conductive layer; forming a first titanium nitride layer over the dielectric layer; and forming a second titanium nitride layer over the first titanium nitride layer, wherein the first titanium nitride layer and the second titanium nitride layer together form a cell electrode.

Claim 2

A method for manufacturing a DRAM capacitor comprising: providing a substrate having field effect transistor formed thereon, wherein the field effect transistor includes a source region and a drain region; forming a first dielectric layer and then an inter-layer dielectric layer over the substrate; etching the inter-layer dielectric layer to form a pattern having a narrow opening; forming a second dielectric layer over the inter-layer dielectric layer; etching the second dielectric layer to form a pattern having a wide opening exposing the narrow opening, then continuing etching down through the first dielectric layer, transferring the pattern on the narrow opening to the first dielectric layer and forming a contact window that exposes a source/drain region; forming a first conductive layer over the substrate covering the wide opening and completely filling the contact window so that the conductive layer is electrically coupled to the exposed source/drain region; removing the second dielectric layer to expose the inter-layer dielectric layer and the conductive layer; forming a dielectric film layer over the exposed first conductive layer; forming a first titanium nitride layer over the dielectric layer; and forming a second titanium nitride layer over the first titanium nitride layer, wherein the first titanium nitride layer and the second titanium nitride layer together form a cell electrode.

Claim 17

A method for forming the cell electrode of a DRAM capacitor, wherein a substrate having a storage electrode formed thereon and a dielectric film layer over the storage electrode is provided, the method comprising: depositing a first titanium nitride layer over the dielectric film layer using a physical vapor deposition process; and depositing a second titanium nitride layer over the first titanium nitride layer using a collimated physical vapor deposition process.

Claim 18

A method for forming the cell electrode of a DRAM capacitor, wherein a substrate having a storage electrode formed thereon and a dielectric film layer over the storage electrode is provided, the method comprising: depositing a first titanium nitride layer over the dielectric film layer using a physical vapor deposition process; and depositing a second titanium nitride layer over the first titanium nitride layer using a collimated physical vapor deposition process.

Claim 22

A method for manufacturing a DRAM capacitor comprising: providing a substrate having a field effect transistor formed thereon, wherein the field effect transistor includes a source region and a drain region; forming a first dielectric layer and then an inter-layer dielectric layer over the substrate; etching the inter-layer dielectric layer to form a pattern having a narrow opening; forming a second dielectric layer over the inter-layer dielectric layer; etching the second dielectric layer to form a pattern having a wide opening exposing the narrow opening, then continuing etching down through the first dielectric layer, transferring the pattern on the narrow opening to the first dielectric layer to form a contact window that exposes a source/drain region; forming a first conductive layer over the substrate covering the wide opening and completely filling the contact window so that the conductive layer is electrically coupled to the exposed source/drain region; removing the second dielectric layer to expose the inter-layer dielectric layer and the conductive layer; forming a dielectric film layer over the exposed first conductive layer; forming a first titanium nitride layer over the dielectric film layer using a physical vapor deposition process; and forming a second titanium nitride layer over the first titanium nitride layer using a collimated physical vapor deposition process resulting in a composite titanium nitride layer that acts as a cell electrode.

Claim 23

A method for manufacturing a DRAM capacitor comprising: providing a substrate having a field effect transistor formed thereon, wherein the field effect transistor includes a source region and a drain region; forming a first dielectric layer and then an inter-layer dielectric layer over the substrate; etching the inter-layer dielectric layer to form a pattern having a narrow opening; forming a second dielectric layer over the inter-layer dielectric layer; etching the second dielectric layer to form a pattern having a wide opening exposing the narrow opening, then continuing etching down through the first dielectric layer, transferring the pattern on the narrow opening to the first dielectric layer to form a contact window that exposes a source/drain region; forming a first conductive layer over the substrate covering the wide opening and completely filling the contact window so that the conductive layer is electrically coupled to the exposed source/drain region; removing the second dielectric layer to expose the inter-layer dielectric layer and the conductive layer; forming a dielectric film layer over the exposed first conductive layer; forming a first titanium nitride layer over the dielectric film layer using a physical vapor deposition process; and forming a second titanium nitride layer over the first titanium nitride layer using a collimated physical vapor deposition process resulting in a composite titanium nitride layer that acts as a cell electrode.