Patent US6083269A successfully refreshed from Google Patents.
US6083269A
Expired / Lapsed
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Digital integrated circuit design system and methodology with hardware
Assignee: Bell Semiconductor LLC
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Filing: 1997-08-19
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Granted: 2000-07-04
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Expires: 2017-08-19
Abstract
Abstract A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.
Inventors
- 👤 Stefan Graef
- 👤 Quang Phan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:57
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
106 words
A method of designing an integrated circuit to ensure hardware testability comprising the steps of: receiving a proposed logic design defined at a behavioral level; defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design and at least one corresponding output vector for verifying operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and prior to logic synthesis, checking the simulation for compliance with the hardware testing rule set.
Claim 2
Independent Claim
106 words
A method of designing an integrated circuit to ensure hardware testability comprising the steps of: receiving a proposed logic design defined at a behavioral level; defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design and at least one corresponding output vector for verifying operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and prior to logic synthesis, checking the simulation for compliance with the hardware testing rule set.
Claim 3
Dependent Claim
64 words
A method according to claim 1 wherein the step of simulating operation of the logic design is carried out on a digital computer using a simulation program stored in a machine-readable medium coupled to the computer and the step of checking the simulation for compliance with the hardware testing rule set also is carried out on a digital computer so it is done automatically.
Claim 4
Dependent Claim
72 words
A method according to claim 2 wherein one of the hardware testing rules requires that each input signal defined by the test bench changes state only at one fixed time offset to the clock signal, and said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that each input signal defined by the test bench changes state only at one fixed time offset to the clock signal.
Claim 5
Dependent Claim
68 words
A method according to claim 2 wherein one of the hardware testing rules requires that each input signal defined by the test bench changes state no more than twice in one clock cycle, and said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that each input signal defined by the test bench changes state no more than twice in one clock cycle.
Claim 6
Dependent Claim
69 words
A method according to claim 2 wherein one of the hardware testing rules requires that the number of input signals does not exceed a predetermined number of timing generators available on the target tester, and said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that the number of input signals does not exceed the number of timing generators available on the target tester.
Claim 7
Dependent Claim
72 words
A method according to claim 2 wherein one of the hardware testing rules requires that a first input vector provides an unknown state for all inputs and a high impedance state for all bidirectional terminals, and said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that the first input vector provides an unknown state for all inputs and a high impedance state for all bidirectional terminals.
Claim 8
Dependent Claim
41 words
A method according to claim 2 wherein said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that none of the test bench vectors exceeds a predetermined vector size specified in the hardware testing rule set.
Claim 9
Dependent Claim
45 words
A method according to claim 2 wherein said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that the number of test vectors does not exceed a predetermined maximum number of test vectors specified in the hardware testing rule set.
Claim 10
Dependent Claim
45 words
A method according to claim 2 wherein said automatically checking the simulation for compliance with the hardware testing rule set includes verifying that a clock speed specified in the simulation does not exceed a predetermined maximum clock speed specified in the hardware testing rule set.
Claim 11
Independent Claim
111 words
A method of designing an integrated circuit to ensure hardware testability comprising the steps of: receiving a circuit design designed at a behavioral level; defining a test bench for simulating operation of the circuit design, the test bench including at least one input vector for stimulating the logic design to verify operation of the circuit design; simulating operation of the circuit using the behavioral level definition and the test bench so as to form simulation results; receiving a predetermined set of one or more hardware testing rules associated with a target tester; and prior to attempting test program generation, checking the simulation results for compliance with the hardware testing rule set.
Claim 12
Independent Claim
111 words
A method of designing an integrated circuit to ensure hardware testability comprising the steps of: receiving a circuit design designed at a behavioral level; defining a test bench for simulating operation of the circuit design, the test bench including at least one input vector for stimulating the logic design to verify operation of the circuit design; simulating operation of the circuit using the behavioral level definition and the test bench so as to form simulation results; receiving a predetermined set of one or more hardware testing rules associated with a target tester; and prior to attempting test program generation, checking the simulation results for compliance with the hardware testing rule set.
Claim 13
Dependent Claim
75 words
A method according to claim 10 wherein checking the simulation results for compliance with the hardware testing rule set includes; providing a predetermined rule checking computer program stored in a machine-readable medium; during the simulating step, executing the rule checking program; during the simulating step, passing indicia of selected simulation events to the rule checker program; and in the rule checker program, checking the indicated simulation events for compliance with the hardware testing rule set.
Claim 14
Dependent Claim
19 words
A method according to claim 11 wherein the hardware testing rule set includes one or more general testing rules.
Claim 15
Dependent Claim
70 words
A method according to claim 10 wherein checking the simulation for compliance with the hardware testing rule set includes; providing a predetermined rule checking computer program stored in a machine-readable medium, the rule-checking program arranged to receive as input a simulation output file; during the simulating step, creating the simulation output file; and after completion of the simulating step, post-processing the simulation output file using the rule checking computer program.
Claim 16
Dependent Claim
19 words
A method according to claim 13 wherein the hardware testing rule set includes one or more general testing rules.
Claim 17
Dependent Claim
24 words
A method according to claim 13 wherein the hardware testing rule set includes one or more testing rules associated with a particular target tester.
Claim 18
Dependent Claim
132 words
A software system for designing an integrated circuit comprising: a description file stored in a computer-readable medium and defining a circuit design at a behavioral level; a test bench file stored in a computer-readable medium and including test vectors defining input logic states for use in simulating operation of the design; a simulation computer program stored in a computer-readable medium and including means for receiving input from the description file and from the test bench file for simulating operation of the circuit responsive to the test bench file, and providing simulation results; a predetermined set of hardware testing rules associated with a target tester for test program generation; and checking means for receiving the simulation results and checking the simulation results against the rule set to determine compliance with the rule set.
Claim 19
Dependent Claim
132 words
A software system for designing an integrated circuit comprising: a description file stored in a computer-readable medium and defining a circuit design at a behavioral level; a test bench file stored in a computer-readable medium and including test vectors defining input logic states for use in simulating operation of the design; a simulation computer program stored in a computer-readable medium and including means for receiving input from the description file and from the test bench file for simulating operation of the circuit responsive to the test bench file, and providing simulation results; a predetermined set of hardware testing rules associated with a target tester for test program generation; and checking means for receiving the simulation results and checking the simulation results against the rule set to determine compliance with the rule set.
Claim 20
Dependent Claim
29 words
A software system according to claim 16 wherein the checking means includes means for post-processing the simulation results so as to check the simulation results against the rule set.
Claim 21
Dependent Claim
20 words
A system according to claim 16 wherein the set of rules includes general rules that support automated test program generation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |