Patent US6081916A successfully refreshed from Google Patents.
US6081916A
Expired / Lapsed
US
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IC with test cells having separate data and test paths
Assignee: Texas Instruments Inc
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Filing: 1997-03-25
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Granted: 2000-06-27
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Expires: 2017-03-25
Abstract
Abstract A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Inventors
- 👤 Lee D. Whetsel, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:01
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318555
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
113 words
A boundary scan test cell comprising: A. a first memory; B. a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; C. a second memory connected to the output of said first memory; and D. a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal; E. wherein said second memory includes inverted and non-inverted outputs, said inverted output is connected as one of said inputs to said first multiplexer, such that a toggled output can be produced by the test cell.
Claim 2
Dependent Claim
113 words
A boundary scan test cell comprising: A. a first memory; B. a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; C. a second memory connected to the output of said first memory; and D. a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal; E. wherein said second memory includes inverted and non-inverted outputs, said inverted output is connected as one of said inputs to said first multiplexer, such that a toggled output can be produced by the test cell.
Claim 3
Dependent Claim
96 words
A boundary scan test cell comprising: A. a first memory; B. a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; C. a second memory connected to the output of said first memory; and D. a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal; E. wherein the output of said first memory is connected as one of said inputs to said first multiplexer.
Claim 4
Dependent Claim
96 words
A boundary scan test cell comprising: A. a first memory; B. a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal; C. a second memory connected to the output of said first memory; and D. a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal; E. wherein the output of said first memory is connected as one of said inputs to said first multiplexer.
Claim 5
Dependent Claim
245 words
An integrated circuit having boundary scan testing, comprising: A. application logic circuitry having one or more inputs and one or more outputs; B. one or more data inputs for receiving data into the integrated circuit; C. one or more data outputs for outputting data from the integrated circuit; D. a test data input for receiving test data into the integrated circuit; E. one or more input test cells connected between respective data inputs and the input or inputs of said application logic circuitry, said input test cells comprising: i. first memory for storing serial data from said test data input; and ii. a second memory connected to said first memory for storing output data; from said first memory and F. one or more output test cells connected between the respective outputs of said application logic and the respective data outputs, each of said output test cells comprising: i. a third memory for storing information from said respective outputs of said application logic circuitry; ii. a fourth memory for storing information output from said third memory; iii. a third multiplexer selectively connecting one of a plurality of inputs thereto to said third memory, one of said plurality of inputs being connected to said test data input; and iv. a fourth multiplexer for selectively connecting one of a plurality of inputs thereto to said data output, the respective output wherein from said application logic and the output of said fourth memory being input to said fourth multiplexer.
Claim 6
Dependent Claim
245 words
An integrated circuit having boundary scan testing, comprising: A. application logic circuitry having one or more inputs and one or more outputs; B. one or more data inputs for receiving data into the integrated circuit; C. one or more data outputs for outputting data from the integrated circuit; D. a test data input for receiving test data into the integrated circuit; E. one or more input test cells connected between respective data inputs and the input or inputs of said application logic circuitry, said input test cells comprising: i. first memory for storing serial data from said test data input; and ii. a second memory connected to said first memory for storing output data; from said first memory and F. one or more output test cells connected between the respective outputs of said application logic and the respective data outputs, each of said output test cells comprising: i. a third memory for storing information from said respective outputs of said application logic circuitry; ii. a fourth memory for storing information output from said third memory; iii. a third multiplexer selectively connecting one of a plurality of inputs thereto to said third memory, one of said plurality of inputs being connected to said test data input; and iv. a fourth multiplexer for selectively connecting one of a plurality of inputs thereto to said data output, the respective output wherein from said application logic and the output of said fourth memory being input to said fourth multiplexer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |