US6081868A
Expired / Lapsed
US
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System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses
Assignee: Hewlett Packard Development Co LP
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Filing: 1998-08-07
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Granted: 2000-06-27
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Expires: 2018-08-07
Abstract
Abstract An integrated diagnostics system within a processing system for monitoring and identifying performance problems within the processing system. The processing system including at least one processor and at least one memory unit, wherein the processor is operable to read one or more addressable memory locations within the memory unit. The integrated diagnostics system including an integrated monitor for counting cache misses and idle time suffered by the processor waiting to read a first addressable memory location within the memory unit.
Inventors
- 👤 Gary S. Brooks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:34
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/32; G06F11/34; G06F11/3409; G06F11/3419; G06F11/3423; G06F11/3466; G06F11/348; G06F11/3495; G06F2201/00; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
213 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for counting cache misses suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; and an illustration for graphically displaying a performance metric gathered during execution of an application program; and wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 2
Dependent Claim
213 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for counting cache misses suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; and an illustration for graphically displaying a performance metric gathered during execution of an application program; and wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 3
Dependent Claim
13 words
The system of claim 1, wherein the illustration includes at least two dimensions.
Claim 4
Dependent Claim
20 words
The system of claim 1, wherein the illustration displays a performance metric as a function of at least one variable.
Claim 5
Dependent Claim
26 words
The system of claim 3, wherein said at least one variable comprises: a code region within said application program; and a thread within said application program.
Claim 6
Dependent Claim
27 words
The system of claim 4, wherein a depiction of the performance metric within the illustration is color coded based on a numerical range of said performance metric.
Claim 7
Dependent Claim
13 words
The system of claim 3, wherein the performance metric is memory cache latency.
Claim 8
Dependent Claim
12 words
The system of claim 3, wherein the performance metric is cache misses.
Claim 9
Dependent Claim
43 words
The system of claim 3, wherein the illustration includes three dimensions, and displays memory latency for a plurality of threads and a plurality of code regions within the application program, wherein different numerical ranges of said memory latency are displayed in different colors.
Claim 10
Independent Claim
160 words
A method of determining performance metrics in a parallel processing system having a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular one of said plurality of processors, said plurality of processors operable to read one or more addressable memory locations within said plurality of memories, comprising the steps of: tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; displaying a performance metric associated with execution of said application program; wherein said step for tracking idle time tracks said idle time for (a) a particular code region of an application, and (b) a particular thread of an application program executing on said parallel processing system.
Claim 11
Independent Claim
160 words
A method of determining performance metrics in a parallel processing system having a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular one of said plurality of processors, said plurality of processors operable to read one or more addressable memory locations within said plurality of memories, comprising the steps of: tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; displaying a performance metric associated with execution of said application program; wherein said step for tracking idle time tracks said idle time for (a) a particular code region of an application, and (b) a particular thread of an application program executing on said parallel processing system.
Claim 12
Dependent Claim
17 words
The method of claim 9, wherein the step of displaying comprises: depicting at least two independent dimensions.
Claim 13
Dependent Claim
29 words
The method of claim 9, comprising the further step of: displaying a performance metric as a function of at least one variable, said performance metric having a numerical range.
Claim 14
Dependent Claim
26 words
The method of claim 11, wherein said at least one variable comprises: a code region within said application program; and a thread within said application program.
Claim 15
Dependent Claim
37 words
The method of claim 12, further comprising the step of: color coding a depiction of said performance metric based on the numerical range of said performance metric for each said code region and for each said thread.
Claim 16
Dependent Claim
13 words
The method of claim 11, wherein the performance metric is memory cache latency.
Claim 17
Dependent Claim
28 words
The method of claim 11, wherein the performance metric is selected from the group consisting of: memory cache latency, cache misses, network cache hits, and memory communication costs.
Claim 18
Dependent Claim
12 words
The method of claim 11, wherein the performance metric is cache misses.
Claim 19
Dependent Claim
210 words
A computer program product having a computer readable medium having computer program logic recorded thereon for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read at least one addressable memory location within said plurality of memory units, the computer program product comprising: a first monitor for counting cache misses suffered by at least one of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by at least one of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; and means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 20
Dependent Claim
210 words
A computer program product having a computer readable medium having computer program logic recorded thereon for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read at least one addressable memory location within said plurality of memory units, the computer program product comprising: a first monitor for counting cache misses suffered by at least one of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by at least one of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; and means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 21
Dependent Claim
32 words
The computer program product of claim 16, further comprising: an illustration for graphically displaying a performance metric gathered during execution of an application program as a function of at least one variable.
References Cited (Backward Citations)
US5845310A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |