US5845310A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and methods for performing cache latency diagnostics in scalable parallel processing architectures including calculating CPU idle time and counting number of cache misses
Assignee: Hewlett Packard Development Co LP
•
Filing: 1996-06-19
•
Granted: 1998-12-01
•
Expires: 2016-06-19
Abstract
Abstract An integrated diagnostics system within a processing system for monitoring and identifying performance problems within the processing system. The processing system including at least one processor and at least one memory unit, wherein the processor is operable to read one or more addressable memory locations within the memory unit. The integrated diagnostics system including an integrated monitor for counting cache misses and idle time suffered by the processor waiting to read a first addressable memory location within the memory unit.
Inventors
- 👤 Gary S. Brooks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:37
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/32; G06F11/34; G06F11/3409; G06F11/3419; G06F11/3423; G06F11/3466; G06F11/348; G06F11/3495; G06F2201/00; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
197 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for counting cache misses suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; and means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 2
Dependent Claim
197 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for counting cache misses suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; a second monitor, integrated with said first monitor, for counting idle time suffered by one or more of said plurality of processors waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses counted by the first monitor to a user of the diagnostics system; and means for reporting an amount of idle time counted by the second monitor to a user of the diagnostics system; wherein each memory of said plurality of memory units is associated with a particular processor of said plurality of processors, said particular processor is operable to access memory units associated with other processors of the plurality of processors.
Claim 3
Dependent Claim
166 words
A diagnostic system for determining performance metrics of an application executing on a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular processor of said plurality of processor, said diagnostic system comprising: means for instrumenting a code region of said application; and means for monitoring performance metrics for said instrumented code region, said means for monitoring comprising: first means for tracking memory cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of memories, wherein said memory cache misses occur at both local and remote memories; and second means for tracking idle time incurred by said one processor from waiting to access said plurality of memories; wherein said mean for monitoring determines said idle time by gating a clock signal of said one processor into a counter, and determines cache misses by causing a control signal to increment said counter.
Claim 4
Dependent Claim
166 words
A diagnostic system for determining performance metrics of an application executing on a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular processor of said plurality of processor, said diagnostic system comprising: means for instrumenting a code region of said application; and means for monitoring performance metrics for said instrumented code region, said means for monitoring comprising: first means for tracking memory cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of memories, wherein said memory cache misses occur at both local and remote memories; and second means for tracking idle time incurred by said one processor from waiting to access said plurality of memories; wherein said mean for monitoring determines said idle time by gating a clock signal of said one processor into a counter, and determines cache misses by causing a control signal to increment said counter.
Claim 5
Dependent Claim
22 words
The diagnostic system of claim 2, wherein said means for monitoring only counts said memory cache misses local to said one processor.
Claim 6
Dependent Claim
22 words
The diagnostic system of claim 2, wherein said means for monitoring only counts said memory cache misses remote from said one processor.
Claim 7
Dependent Claim
22 words
The diagnostic system of claim 2, wherein said means for monitoring determines said performance metrics for a particular thread of said application.
Claim 8
Dependent Claim
40 words
The diagnostic system of claim 2, wherein the performance monitoring means further comprises: means for reporting an amount of cache misses tracked by the first monitor; and means for reporting an amount of idle time tracked by the second monitor.
Claim 9
Dependent Claim
22 words
The diagnostic system of claim 2, wherein: the particular processor can access memories associated with other processors of the plurality of processors.
Claim 10
Dependent Claim
178 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and a second monitor, integrated with said first monitor, for tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses tracked by the first monitor; and means for reporting an amount of idle time tracked by the second monitor; wherein each memory of said plurality of memories is associated with a particular processor of said plurality of processors, said particular processor is operable to access memories associated with other processors of the plurality of processors.
Claim 11
Dependent Claim
178 words
A diagnostics system for use in a parallel processing system, said parallel processing system including a plurality of processors and a plurality of memory units, said plurality of processors operable to read one or more addressable memory locations within said plurality of memory units, said diagnostics system comprising: a first monitor for tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and a second monitor, integrated with said first monitor, for tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; means for reporting an amount of cache misses tracked by the first monitor; and means for reporting an amount of idle time tracked by the second monitor; wherein each memory of said plurality of memories is associated with a particular processor of said plurality of processors, said particular processor is operable to access memories associated with other processors of the plurality of processors.
Claim 12
Dependent Claim
23 words
The diagnostic system of claim 8, wherein said first monitor tracks said cache misses by causing a control signal to increment a counter.
Claim 13
Dependent Claim
34 words
The diagnostic system of claim 8, wherein said first and second monitors track said cache misses and said idle time for a particular code region of an application executing on said parallel processing system.
Claim 14
Dependent Claim
33 words
The diagnostic system of claim 8, wherein said first and second monitors track said cache misses and said idle time for a particular thread of an application executing on said parallel processing system.
Claim 15
Dependent Claim
20 words
The diagnostic system of claim 8, wherein said first monitor only counts said cache misses local to said one processor.
Claim 16
Dependent Claim
20 words
The diagnostic system of claim 8, wherein said first monitor only counts said cache misses remote from said one processor.
Claim 17
Dependent Claim
26 words
The diagnostic system of claim 8, wherein said second monitor tracks said idle time by gating a clock signal of said one processor into a counter.
Claim 18
Independent Claim
147 words
A method of determining performance metrics in a parallel processing system having a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular one of said plurality of processors, said plurality of processors operable to read one or more addressable memory locations within said plurality of memories, comprising the steps of: tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; wherein said step for tracking idle time tracks said idle time for (a) a particular code region of an application, and (b) a particular thread of and application executing on said parallel processing.
Claim 19
Independent Claim
147 words
A method of determining performance metrics in a parallel processing system having a plurality of processors and a plurality of memories, each memory of said plurality of memories associated with a particular one of said plurality of processors, said plurality of processors operable to read one or more addressable memory locations within said plurality of memories, comprising the steps of: tracking cache misses incurred by at least one processor of said plurality of processors in accessing said plurality of addressable memory units, wherein said cache misses occur at both local and remote addressable memory units; and tracking idle time incurred by said one processor from waiting to access said plurality of addressable memory units; wherein said step for tracking idle time tracks said idle time for (a) a particular code region of an application, and (b) a particular thread of and application executing on said parallel processing.
Claim 20
Dependent Claim
21 words
The method of claim 15, wherein said step for tracking cache misses only tracks cache misses local to said one processor.
Claim 21
Dependent Claim
21 words
The method of claim 15, wherein said step for tracking cache misses only tracks cache misses remote from said one processor.
Claim 22
Dependent Claim
39 words
The method of claim 15, further comprising the steps of: accessing, by the particular processor, the memory associated with the particular processor; and accessing, by the particular processor, a memory associated with another processor of the plurality of processors.
Claim 23
Dependent Claim
33 words
The method of claim 15, further comprising the steps of: reporting an amount of cache misses tracked by the first monitor; and reporting an amount of idle time tracked by the second monitor.
References Cited (Backward Citations)
US4464712A
Cited
US4885680A
Cited
US5384906A
Cited
US5239641A
Cited
US5072376A
Cited
US5097437A
Cited
US5072418A
Cited
US5392436A
Cited
US5581745A
Cited
US5247653A
Cited
US5325499A
Cited
US5463775A
Cited
US5386526A
Cited
US5287508A
Cited
US5398325A
Cited
US5361391A
Cited
US5537541A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-30 | 2002-06-01 | 2002-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-30 | 2006-06-01 | 2006-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-30 | 2010-06-01 | 2010-12-01 | $7700.00 | Window Closed / Lapsed |