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US6078736A
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Method of designing FPGAs for dynamically reconfigurable computing
Assignee: Xilinx Inc
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Filing: 1997-08-28
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Granted: 2000-06-20
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Expires: 2017-08-28
Abstract
Abstract A method of designing FPGAs for reconfigurable computing comprises a software environment for reconfigurable coprocessor applications. This environment comprises a standard high level language compiler (i.e. Java) and a set of libraries. The FPGA is configured directly from a host processor, configuration, reconfiguration and host run-time operation being supported in a single piece of code. Design compile times on the order of seconds and built-in support for parameterized cells are significant features of the inventive method.
Inventors
- 👤 Steven A. Guccione
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 12:16
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
108 words
A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby; the method comprising the steps of: a) programming the host processor with instructions in a high level programming language; b) instantiating elements from a library of elements compatible with the high level programming language; c) providing a compiler for the high level programming language to the host processor for generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information; and d) configuring the FPGA from the host processor in response to the executable code.
Claim 2
Independent Claim
108 words
A method of configuring a field programmable gate array (FPGA), the FPGA being connected to a host processor for configuration thereby; the method comprising the steps of: a) programming the host processor with instructions in a high level programming language; b) instantiating elements from a library of elements compatible with the high level programming language; c) providing a compiler for the high level programming language to the host processor for generating executable code in response to the programmed instructions and the instantiated library elements, the executable code including compiled placement and routing information; and d) configuring the FPGA from the host processor in response to the executable code.
Claim 3
Dependent Claim
15 words
The method recited in claim 1 wherein the FPGA is used for dynamically reconfigurable computing.
Claim 4
Dependent Claim
16 words
The method recited in claim 1 or claim 2 wherein the high level language is Java.
Claim 5
Dependent Claim
16 words
The method recited in claim 1 or claim 2 wherein the library comprises combinational logic elements.
Claim 6
Dependent Claim
15 words
The method recited in claim 1 or claim 2 wherein the library comprises flip-flop elements.
Claim 7
Dependent Claim
15 words
The method recited in claim 1 or claim 2 wherein the library comprises latch elements.
Claim 8
Dependent Claim
24 words
The method recited in claim 1 or claim 2 further comprising the step of: e) using the library elements to generate a parameterized cell.
Claim 9
Dependent Claim
21 words
The method recited in claim 7 wherein the cell is a counter parameterized by the number of bits in the counter.
Claim 10
Independent Claim
89 words
A method of configuring a field programmable gate array (FPGA) for dynamically reconfigurable computing; the method comprising the steps of: a) programming a host processor with instructions in a high level language; b) providing a compiler for the high level programming language running on the host processor for generating executable code in response to the instructions, the executable code including compiled placement and routing information; and c) connecting the host processor to the FPGA for dynamic reconfiguration programming of the FPGA by the host processor via the executable code.
Claim 11
Independent Claim
89 words
A method of configuring a field programmable gate array (FPGA) for dynamically reconfigurable computing; the method comprising the steps of: a) programming a host processor with instructions in a high level language; b) providing a compiler for the high level programming language running on the host processor for generating executable code in response to the instructions, the executable code including compiled placement and routing information; and c) connecting the host processor to the FPGA for dynamic reconfiguration programming of the FPGA by the host processor via the executable code.
Claim 12
Dependent Claim
13 words
The method recited in claim 9 wherein the high level language is Java.
Claim 13
Dependent Claim
23 words
The method recited in claim 9 further comprising the step of: d) instantiating elements from a library of elements compatible with the compiler.
Claim 14
Dependent Claim
13 words
The method recited in claim 11 wherein the library comprises combinational logic elements.
Claim 15
Dependent Claim
12 words
The method recited in claim 11 wherein the library comprises flip-flop elements.
Claim 16
Dependent Claim
12 words
The method recited in claim 11 wherein the library comprises latch elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-20 | 2003-12-20 | 2004-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-20 | 2007-12-20 | 2008-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-20 | 2011-12-20 | 2012-06-20 | $7700.00 | Window Closed / Lapsed |