Patent US6077763A successfully refreshed from Google Patents.
US6077763A
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Process for fabricating a self-aligned contact
Assignee: United Microelectronics Corp
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Filing: 1996-11-19
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Granted: 2000-06-20
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Expires: 2016-11-19
Abstract
Abstract A process of fabricating self-aligned contacts for a semiconductor memory IC device. The substrate of the memory device has formed thereon gate structures of the memory cell units for the memory device. The gate structures are regularly spaced apart by first sidewall spacers formed on sidewalls of the gate structures. Source/drain regions of the memory cell units are formed in the device substrate in regions between consecutive gate structures. The process includes first forming an insulating layer over the surface of the substrate, followed by anisotropically etching back the insulating layer until a predetermined thickness over and normal to the top surface of the gate structure is obtained. A photoresist layer is formed over the surface of the insulating layer, with openings exposing contact regions for the memory cell units. Second sidewall spacers are then formed on the sidewalls of the gate structures and the source/drain regions are exposed, by etching into the insulating layer through the openings. The second sidewall spacers cover the first sidewall spacers. Contacts are then formed for the memory cell units, in direct electrical contact with the source/drain regions.
Inventors
- 👤 Hwi-Huang Chen
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10B; H10B20/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
193 words
A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate, wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell units of the memory device, the gate structures having upper surfaces above a substrate surface and sidewalls between the upper surfaces and the substrate surface, first sidewall spacers being located on sidewalls of the gate structures, and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures; the process comprising: forming an insulating layer over the substrate surface; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate; forming a photoresist layer over a surface of the insulating layer, with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions.
Claim 2
Dependent Claim
193 words
A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate, wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell units of the memory device, the gate structures having upper surfaces above a substrate surface and sidewalls between the upper surfaces and the substrate surface, first sidewall spacers being located on sidewalls of the gate structures, and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures; the process comprising: forming an insulating layer over the substrate surface; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate; forming a photoresist layer over a surface of the insulating layer, with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions.
Claim 3
Dependent Claim
24 words
The process of fabricating self-aligned contacts of claim 1, wherein the insulating layer is formed abutting the gate structures and the first sidewall spacers.
Claim 4
Dependent Claim
28 words
The process of fabricating self-aligned contacts of claim 2, wherein the insulating layer is a silicon oxide layer with a thickness in the range of about 3,000-6,000 Å.
Claim 5
Dependent Claim
56 words
The process of fabricating self-aligned contacts of claim 3, wherein said anisotropically etching back the insulating layer includes anisotropically etching back the silicon oxide layer to consume a surface layer having a thickness over the top surface of the gate structure in a direction normal to the top surface in the range of about 800-2,000 Å.
Claim 6
Dependent Claim
18 words
The process of fabricating self-aligned contacts of claim 1, wherein the contacts are formed of a polysilicon layer.
Claim 7
Dependent Claim
18 words
The process of fabricating self-aligned contacts of claim 1, wherein the contacts are formed of a polycide layer.
Claim 8
Dependent Claim
32 words
The process of fabricating self-aligned contact of claim 1, wherein each of the plurality of gate structures comprises a gate dielectric layer, a gate electrode, and a silicon oxide layer, stacked successively.
Claim 9
Dependent Claim
25 words
The process of fabricating self-aligned contact of claim 1, wherein each of the source/drain regions comprises a heavily-doped region enclosed by a larger lightly-doped region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-20 | 2003-12-20 | 2004-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-20 | 2007-12-20 | 2008-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-20 | 2011-12-20 | 2012-06-20 | $7700.00 | Window Closed / Lapsed |