Method for fabricating a transistor gate with a T-like structure

Claim 1

A method for fabricating a T-like gate, the method comprising: forming a pad oxide layer over a semiconductor substrate; forming a hard layer on the pad oxide layer; patterning the hard layer to form an opening in the hard layer to expose a portion of the pad oxide layer; forming a stopper layer over the substrate, wherein the stopper layer at least covers the exposed portion of the pad oxide layer; depositing a dielectric layer over the substrate, wherein the dielectric layer also covers an inner peripheral surface of the opening; removing the dielectric layer other than the portion on each sidewall of the opening so that the remaining dielectric layer covers the inner peripheral surface of the opening; removing a top portion of the remaining dielectric layer on each sidewall of the opening and a bottom portion of the remaining dielectric layer so that the opening has a T-like free space and the stopper layer within the opening is exposed; removing the stopper layer to expose the pad oxide layer within the opening; removing the exposed portion of the pad oxide layer to expose the substrate; forming a gate oxide layer on the exposed substrate within the opening; forming a polysilicon layer to fill the T-like free space of the opening, wherein the polysilicon layer and the remaining dielectric layer contact each other; removing the hard layer to expose a top portion of the polysilicon layer; forming a titanium metal over the substrate; forming a titanium nitride layer over the titanium metal layer; performing a first thermal process to form a self-aligned titanium silicide at least over the exposed top portion of the polysilicon layer; removing the remaining titanium metal layer and the remaining titanium nitride layer through a selective etching process; removing the remaining dielectric layer so that the T-like gate is formed, wherein a lower portion of the polysilicon layer originally covered by the remaining dielectric layer is exposed; and performing a second thermal process to reform a crystal structure of the titanium silicide layer so as to reduce its resistance.

Claim 2

A method for fabricating a T-like gate, the method comprising: forming a pad oxide layer over a semiconductor substrate; forming a hard layer on the pad oxide layer; patterning the hard layer to form an opening in the hard layer to expose a portion of the pad oxide layer; forming a stopper layer over the substrate, wherein the stopper layer at least covers the exposed portion of the pad oxide layer; depositing a dielectric layer over the substrate, wherein the dielectric layer also covers an inner peripheral surface of the opening; removing the dielectric layer other than the portion on each sidewall of the opening so that the remaining dielectric layer covers the inner peripheral surface of the opening; removing a top portion of the remaining dielectric layer on each sidewall of the opening and a bottom portion of the remaining dielectric layer so that the opening has a T-like free space and the stopper layer within the opening is exposed; removing the stopper layer to expose the pad oxide layer within the opening; removing the exposed portion of the pad oxide layer to expose the substrate; forming a gate oxide layer on the exposed substrate within the opening; forming a polysilicon layer to fill the T-like free space of the opening, wherein the polysilicon layer and the remaining dielectric layer contact each other; removing the hard layer to expose a top portion of the polysilicon layer; forming a titanium metal over the substrate; forming a titanium nitride layer over the titanium metal layer; performing a first thermal process to form a self-aligned titanium silicide at least over the exposed top portion of the polysilicon layer; removing the remaining titanium metal layer and the remaining titanium nitride layer through a selective etching process; removing the remaining dielectric layer so that the T-like gate is formed, wherein a lower portion of the polysilicon layer originally covered by the remaining dielectric layer is exposed; and performing a second thermal process to reform a crystal structure of the titanium silicide layer so as to reduce its resistance.

Claim 14

The method of claim Is wherein the step of forming the polysilicon layer to fill the T-like free space of the opening further comprises: depositing a primary polysilicon layer over the substrate; and performing a chemical mechanical polishing (CMP) process to planarize the primary polysilicon and again expose the hard layer.

Claim 22

A method for fabricating a T-like gate on a semiconductor substrate having a pad oxide layer and a hard layer sequentially formed over the substrate, the method comprising: patterning the hard layer to form an opening in the hard layer, wherein the opening exposes the pad oxide layer; depositing a stopper layer over the substrate, wherein the stopper layer at least covers a bottom surface of the opening; forming a dielectric sidewall layer on each sidewall of the opening at a lower portion so that the opening has a T-like free space, wherein the stopper layer is used as an etching stop during forming the dielectric sidewall layer; removing the stopper layer to expose the pad oxide layer within the opening; removing the exposed portion of the pad oxide layer to expose the substrate; forming a gate oxide layer on the exposed substrate within the opening; forming a polysilicon layer to fill the T-like free space of the opening, wherein the polysilicon layer and the dielectric sidewall layer contact each other; removing the hard layer to expose a top portion of the polysilicon layer; forming a self-aligned silicide at least over the exposed top portion of the polysilicon layer; removing the dielectric sidewall layer so that the T-like gate is formed, wherein a lower portion of the polysilicon layer originally covered by the dielectric sidewall layer is exposed; and performing a second thermal process to reform a crystal structure of the titanium silicide layer so as to reduce its resistance.

Claim 23

A method for fabricating a T-like gate on a semiconductor substrate having a pad oxide layer and a hard layer sequentially formed over the substrate, the method comprising: patterning the hard layer to form an opening in the hard layer, wherein the opening exposes the pad oxide layer; depositing a stopper layer over the substrate, wherein the stopper layer at least covers a bottom surface of the opening; forming a dielectric sidewall layer on each sidewall of the opening at a lower portion so that the opening has a T-like free space, wherein the stopper layer is used as an etching stop during forming the dielectric sidewall layer; removing the stopper layer to expose the pad oxide layer within the opening; removing the exposed portion of the pad oxide layer to expose the substrate; forming a gate oxide layer on the exposed substrate within the opening; forming a polysilicon layer to fill the T-like free space of the opening, wherein the polysilicon layer and the dielectric sidewall layer contact each other; removing the hard layer to expose a top portion of the polysilicon layer; forming a self-aligned silicide at least over the exposed top portion of the polysilicon layer; removing the dielectric sidewall layer so that the T-like gate is formed, wherein a lower portion of the polysilicon layer originally covered by the dielectric sidewall layer is exposed; and performing a second thermal process to reform a crystal structure of the titanium silicide layer so as to reduce its resistance.