Patent US6073264A successfully refreshed from Google Patents.
US6073264A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Debug vector launch tool
Assignee: Intel Corp
•
Filing: 1998-04-02
•
Granted: 2000-06-06
•
Expires: 2018-04-02
Abstract
Abstract The present invention discloses a debug tool to provide a test vector to a device under test. The debug tool comprises: (1) a pattern generator unit coupled to the device under test to transmit the test vector to the device under test and to generate a master triggering signal; (2) a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector; and (3) a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test.
Inventors
- 👤 Mark B. Nelson
- 👤 Richard F. Clark
- 👤 Ken R. Watrobski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318307; G01R31/31705; G01R31/319; G01R31/3193; G01R31/31935
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
135 words
A debug tool to provide a test vector to a device under test, the debug tool comprising: a pattern generator unit coupled to the device under test to transmit the test vector to the device under test, the pattern generator unit generating a master triggering signal; a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector; and a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 2
Dependent Claim
135 words
A debug tool to provide a test vector to a device under test, the debug tool comprising: a pattern generator unit coupled to the device under test to transmit the test vector to the device under test, the pattern generator unit generating a master triggering signal; a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector; and a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 3
Dependent Claim
42 words
The debug tool of claim 1 further comprises: a processor coupled to the pattern generator unit, the waveform acquisition unit, and the trigger unit to perform a control function on the pattern generator unit, the waveform acquisition unit, and the trigger unit.
Claim 4
Dependent Claim
21 words
The debug tool of claim 2 wherein the pattern generator unit comprises a test vector memory to store the test vector.
Claim 5
Dependent Claim
39 words
The debug tool of claim 2 wherein the waveform acquisition unit further receives a second test output, the second test output being generated by a signal acquisition instrument, the signal acquisition instrument being coupled to the device under test.
Claim 6
Dependent Claim
60 words
The debug tool of claim 4 wherein the waveform acquisition unit further comprises: a capture and logic circuit to capture one of the first and second test outputs and produce a digital word representative of one of the first and second test outputs; and an acquisition memory module coupled to the capture and logic circuit to store the digital word.
Claim 7
Dependent Claim
53 words
The debug tool of claim 5 wherein the capture and logic circuit further comprises: a sample-and-hold device to sample and hold one of the first and second test outputs; and an analog-to-digital converter coupled to the sample-and-hold device to convert the one of the first and second test outputs to the digital word.
Claim 8
Dependent Claim
31 words
The debug tool of claim 5 wherein the capture and logic circuit further comprises: a logic circuit to perform a plurality of logic functions on the first and second test outputs.
Claim 9
Dependent Claim
25 words
The debug tool of claim 2 wherein the trigger unit further comprises a frequency generator to generate a synchronizing signal based on a signal specification.
Claim 10
Dependent Claim
46 words
The debug tool of claim 8 wherein the control function is one of a downloading of the test vector from a design file to the test vector memory module, a generation of the signal specification, and a reading of the captured first and second test outputs.
Claim 11
Dependent Claim
14 words
The debug tool of claim 8 wherein the frequency generator operates at 1 GHz.
Claim 12
Independent Claim
166 words
A system to provide a test vector to a device under test, the system comprising: a host processor; a memory coupled to the host processor, the memory containing program instructions executed by the host processor; and a debug tool coupled to the host processor, the debugging tool comprising: a pattern generator unit coupled to the device under test to transmit the test vector to the device under test, the pattern generator unit generating a master triggering signal, a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector, and a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 13
Independent Claim
166 words
A system to provide a test vector to a device under test, the system comprising: a host processor; a memory coupled to the host processor, the memory containing program instructions executed by the host processor; and a debug tool coupled to the host processor, the debugging tool comprising: a pattern generator unit coupled to the device under test to transmit the test vector to the device under test, the pattern generator unit generating a master triggering signal, a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector, and a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 14
Dependent Claim
38 words
The system of claim 11 wherein the waveform acquisition unit further receives a second test output, the second test output being generated by a signal acquisition instrument, the signal acquisition instrument being coupled to the device under test.
Claim 15
Dependent Claim
59 words
The system of claim 11 wherein the waveform acquisition unit further comprises: a capture and logic circuit to capture one of the first and second test outputs and produce a digital word representative of one of the first and second test outputs; and an acquisition memory module coupled to the capture and logic circuit to store the digital word.
Claim 16
Dependent Claim
18 words
The system of claim 13 wherein the program instructions executed by the host processor read the digital word.
Claim 17
Dependent Claim
15 words
The system of claim 15 wherein the digital word is compared with a simulated output.
Claim 18
Dependent Claim
21 words
The system of claim 11 wherein the program instructions executed by the host processor control an operation of the debug tool.
Claim 19
Independent Claim
104 words
A method for providing a test vector to a device under test, the method comprising the steps of: transmitting the test vector to the device under test by a pattern generator unit; generating a master triggering signal to a trigger unit; receiving a first test output from the device under test by a waveform acquisition unit, the first test output being generated by the device under test in response to the transmitted test vector; and synchronizing the pattern generator unit, the waveform acquisition unit, and device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 20
Independent Claim
104 words
A method for providing a test vector to a device under test, the method comprising the steps of: transmitting the test vector to the device under test by a pattern generator unit; generating a master triggering signal to a trigger unit; receiving a first test output from the device under test by a waveform acquisition unit, the first test output being generated by the device under test in response to the transmitted test vector; and synchronizing the pattern generator unit, the waveform acquisition unit, and device under test using one of the mastering triggering signal and a synchronizing signal from the device under test.
Claim 21
Dependent Claim
37 words
The method of claim 17, prior to transmitting the test vector, further comprises: downloading the test vector from a design file; and storing the test vector in a test vector memory module in the pattern generator unit.
Claim 22
Dependent Claim
16 words
The method of claim 17 further comprises comparing the first test output with a simulated output.
Claim 23
Dependent Claim
23 words
The method of claim 19 wherein the simulated output is time adjusted to compensate for a delay caused by the device under test.
References Cited (Backward Citations)
US5289116A
Cited
US5412662A
Cited
US5463639A
Cited
US5508607A
Cited
US5731984A
Cited
US5854804A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |