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US6073261A
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Circuit for evaluating signal timing
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-05-22
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Granted: 2000-06-06
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Expires: 2018-05-22
Abstract
Abstract The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with this inventive aspect, the method includes the steps of selecting a first electrical signal to be evaluated and discretizing the selected electrical signal into a plurality of signal values closely spaced in time. This "discretizing" function is preferably achieved passing the selected signal through a plurality of cascaded delay or buffer elements, then loading the signal values output from each buffer element (at a given time instance) into a plurality of register elements. In this way, the register elements, collectively, contain a snapshot of the selected signal over a defined period of time. Finally, the method includes the step of evaluating the plurality of signal values.
Inventors
- 👤 Brian C. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31937; G01R31/30; G01R31/3016
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
78 words
A circuit for evaluating the timing relationship of electrical signals in an integrated circuit comprising: a signal select circuit having an output, the signal select circuit configured to select a signal for evaluation and direct it to the output; a plurality of signal buffers electrically cascaded to the output of the signal select circuit; and a scan chain having a plurality of scan elements disposed to acquire a state of electrical signals along the plurality of signal buffers.
Claim 2
Dependent Claim
78 words
A circuit for evaluating the timing relationship of electrical signals in an integrated circuit comprising: a signal select circuit having an output, the signal select circuit configured to select a signal for evaluation and direct it to the output; a plurality of signal buffers electrically cascaded to the output of the signal select circuit; and a scan chain having a plurality of scan elements disposed to acquire a state of electrical signals along the plurality of signal buffers.
Claim 3
Dependent Claim
26 words
The circuit as defined in claim 1, wherein the signal select circuit is a multiplexer circuit having a plurality of signal inputs and a signal output.
Claim 4
Dependent Claim
25 words
The circuit as defined in claim 1, further including a circuit configured to shift out of the electrical signal values acquired in the scan chain.
Claim 5
Dependent Claim
27 words
The circuit as defined in claim 1, further including a circuit configured to controllably select the electrical signal directed to the output of the signal select circuit.
Claim 6
Dependent Claim
32 words
The circuit as defined in claim 2, wherein the inputs of the signal select circuit are electrically connected to a plurality of circuit nodes having signals that are desired to be evaluated.
Claim 7
Dependent Claim
13 words
The circuit as defined in claim 1, wherein the signal buffers are inverters.
Claim 8
Dependent Claim
23 words
The circuit as defined in claim 1, further including a circuit configured to select at least two signals for comparison with one another.
Claim 9
Dependent Claim
18 words
The circuit as defined in claim 6, wherein the inverters are implemented in a pair of field-effect transistors.
Claim 10
Dependent Claim
56 words
A circuit for evaluating the timing relationship of electrical signals in an integrated circuit comprising: means for selecting a signal for evaluation, the signal selected from a plurality of input signals; means for discretizing the selected signal into a plurality of samples closely spaced in time; and means for acquiring the discretized selected signal for evaluation.
Claim 11
Dependent Claim
56 words
A circuit for evaluating the timing relationship of electrical signals in an integrated circuit comprising: means for selecting a signal for evaluation, the signal selected from a plurality of input signals; means for discretizing the selected signal into a plurality of samples closely spaced in time; and means for acquiring the discretized selected signal for evaluation.
Claim 12
Dependent Claim
14 words
The circuit as defined in claim 9, means for selecting includes a multiplexer circuit.
Claim 13
Dependent Claim
27 words
The circuit as defined in claim 9, means for discretizing the selected signal includes a plurality of buffers cascaded with the output of the means for selecting.
Claim 14
Dependent Claim
21 words
The circuit as defined in claim 9, means for acquiring includes a scan chain having a plurality of registered circuit components.
Claim 15
Independent Claim
48 words
A method for evaluating the timing relationship of electrical signals in an integrated circuit comprising the steps of: selecting a first electrical signal to be evaluated; discretizing the selected electrical signal into a plurality of signal values closely spaced in time; and evaluating the plurality of signal values.
Claim 16
Independent Claim
48 words
A method for evaluating the timing relationship of electrical signals in an integrated circuit comprising the steps of: selecting a first electrical signal to be evaluated; discretizing the selected electrical signal into a plurality of signal values closely spaced in time; and evaluating the plurality of signal values.
Claim 17
Dependent Claim
23 words
The method as defined in claim 13, wherein the step of selecting a first electrical signal includes routing a signal through a multiplexer.
Claim 18
Dependent Claim
28 words
The circuit as defined in claim 13, wherein the step of discretizing the selected signal creates a plurality of time-spaced signal values that characterize the selected electrical signal.
Claim 19
Dependent Claim
30 words
The circuit as defined in claim 13, wherein the step of discretizing the selected signal includes the step of passing the selected signal through a plurality of cascaded circuit elements.
Claim 20
Dependent Claim
13 words
The circuit as defined in claim 16, wherein the circuit elements are inverters.
Claim 21
Dependent Claim
27 words
The circuit as defined in claim 13, further including the step of transferring the discretized signal into a plurality of register elements that form a scan chain.
Claim 22
Dependent Claim
19 words
The circuit as defined in claim 13, further including the step of selecting a second electrical signal for evaluation.
Claim 23
Dependent Claim
26 words
The circuit as defined in claim 19, further including the step of discretizing the second signal into a plurality of signal values closely spaced in time.
Claim 24
Dependent Claim
22 words
The circuit as defined in claim 20, further including the step of evaluating the second signal in relation to the first signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |