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US6072199A
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Insulated gate bipolar transistor
Assignee: Fuji Electric Co Ltd
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Filing: 1993-11-12
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Granted: 2000-06-06
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Expires: 2013-11-12
Abstract
Abstract A insulated gate bipolar transistor comprising a semiconductor substrate layer having an impurity concentration of not less than 4.0×10 13 /cm 3 , and being substantially free of lifetime killers.
Inventors
- 👤 Noriyuki Iwamuro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:33
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/60
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
164 words
A semiconductor element, comprising: a substrate of first conductivity type having an impurity concentration of not less than 4.0×10 13 /cm 3 , said substrate being produced from a single silicon crystal prepared by a zone melting method and substantially free of lifetime killers; a first diffused region of second conductivity type in a first surface of the substrate; a second diffused region of first conductivity type in the first region such that a channel region is formed between the second region and the substrate through the first region; an insulating film on the first surface of the substrate over the channel region; a gate electrode on the insulating film; a source electrode on the first surface of the substrate in contact with the first and second regions; a third diffused region of second conductivity type formed in an opposite second surface of the substrate and having a depth of at least 2 microns; and a drain electrode in contact with said third region.
Claim 2
Dependent Claim
164 words
A semiconductor element, comprising: a substrate of first conductivity type having an impurity concentration of not less than 4.0×10 13 /cm 3 , said substrate being produced from a single silicon crystal prepared by a zone melting method and substantially free of lifetime killers; a first diffused region of second conductivity type in a first surface of the substrate; a second diffused region of first conductivity type in the first region such that a channel region is formed between the second region and the substrate through the first region; an insulating film on the first surface of the substrate over the channel region; a gate electrode on the insulating film; a source electrode on the first surface of the substrate in contact with the first and second regions; a third diffused region of second conductivity type formed in an opposite second surface of the substrate and having a depth of at least 2 microns; and a drain electrode in contact with said third region.
Claim 3
Dependent Claim
30 words
The semiconductor element according to claim 1, comprising a high impurity concentration buffer fourth diffused region of first conductivity type in the substrate beyond and adjacent to the third region.
Claim 4
Dependent Claim
18 words
The semiconductor element according to claim 1, wherein the zone melting method is a floating zone melting process.
Claim 5
Dependent Claim
15 words
The semiconductor element according to claim 1, wherein the substrate is approximately 200 microns thick.
Claim 6
Dependent Claim
70 words
An insulated gate bipolar transistor comprising: a semiconductor substrate of first conductivity type having an impurity concentration of not less than 4.0×10 13 /cm 3 , and being produced from a single silicon crystal prepared by a zone melting method and substantially free of lifetime killers; and a diffused region of second conductivity type formed in a surface of the substrate and having a depth of at least 2 microns.
Claim 7
Dependent Claim
70 words
An insulated gate bipolar transistor comprising: a semiconductor substrate of first conductivity type having an impurity concentration of not less than 4.0×10 13 /cm 3 , and being produced from a single silicon crystal prepared by a zone melting method and substantially free of lifetime killers; and a diffused region of second conductivity type formed in a surface of the substrate and having a depth of at least 2 microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |