US6069063A
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US
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Method to form polysilicon resistors shielded from hydrogen intrusion
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-04-01
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Granted: 2000-05-30
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Expires: 2019-04-01
Abstract
Abstract A method to form polysilicon resistors shielded from hydrogen intrusion is described. A semiconductor substrate is provided. Field oxide isolation regions are provided overlying the substrate. A polysilicon layer is deposited overlying the field oxide regions and the substrate. The polysilicon layer is etched away where it is not covered by a mask to form a polysilicon resistor. An interlevel dielectric layer is deposited overlying the polysilicon resistor. Nitrogen ions are implanted into the interlevel dielectric layer. The interlevel dielectric layer is annealed to form a silicon oxynitride shield layer in the interlevel dielectric layer. Contact openings are etched through the interlevel dielectric layer to the polysilicon resistor. The contact openings are filled with a metal layer. The metal layer is patterned. The patterned metal layer is covered with a passivation layer wherein the passivation layer contains hydrogen atoms and wherein the silicon oxynitride shield layer prevents hydrogen atoms from penetrating the polysilicon resistor. The integrated circuit is completed.
Inventors
- 👤 Juin-Jie Chang
- 👤 Shih-Chi Lin
- 👤 Yen-Ming Chen
- 👤 Yung-Lung Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:11
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6927; H10D; H10D1/00; H10D1/40; H10D1/47; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6524; H10P14/6526; H10P14/69215; H10P30/00; H10P30/40; H10P32/00; H10P32/20
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
147 words
A method of forming a polysilicon resistor in an integrated circuit comprising: providing a semiconductor substrate; providing field oxide isolation regions overlying said substrate; depositing a polysilicon layer overlying said field oxide regions and said substrate; etching said polysilicon layer where it is not covered by a mask to form a polysilicon resistor; depositing an interlevel dielectric layer overlying said polysilicon resistor; implanting nitrogen ions into said interlevel dielectric layer; annealing said interlevel dielectric layer to form a silicon oxynitride shield layer in said interlevel dielectric layer; etching contact openings through said interlevel dielectric layer to said polysilicon resistor; filling said contact openings with a metal layer; patterning said metal layer; covering said patterned metal layer with a passivation layer wherein said passivation layer contains hydrogen atoms and wherein said silicon oxynitride shield layer prevents hydrogen atoms from penetrating said polysilicon resistor; and completing said integrated circuit.
Claim 2
Independent Claim
147 words
A method of forming a polysilicon resistor in an integrated circuit comprising: providing a semiconductor substrate; providing field oxide isolation regions overlying said substrate; depositing a polysilicon layer overlying said field oxide regions and said substrate; etching said polysilicon layer where it is not covered by a mask to form a polysilicon resistor; depositing an interlevel dielectric layer overlying said polysilicon resistor; implanting nitrogen ions into said interlevel dielectric layer; annealing said interlevel dielectric layer to form a silicon oxynitride shield layer in said interlevel dielectric layer; etching contact openings through said interlevel dielectric layer to said polysilicon resistor; filling said contact openings with a metal layer; patterning said metal layer; covering said patterned metal layer with a passivation layer wherein said passivation layer contains hydrogen atoms and wherein said silicon oxynitride shield layer prevents hydrogen atoms from penetrating said polysilicon resistor; and completing said integrated circuit.
Claim 3
Dependent Claim
22 words
The method according to claim 1 wherein said polysilicon layer is formed to a thickness of between about 2000 and 4000 Angstroms.
Claim 4
Dependent Claim
112 words
The method according to claim 1 after said step of depositing said polysilicon layer further comprising: growing a first silicon dioxide layer on said polysilicon layer; implanting first ions through said first dioxide layer into said polysilicon layer to dope said polysilicon layer; depositing a capping oxide layer overlying said first oxide layer and patterning said capping oxide layer and said first oxide layer to cover planned said polysilicon resistor; implanting second ions into said polysilicon layer to provide gate doping wherein said capping oxide layer over planned said polysilicon resistor prevents said second ions from penetrating planned said resistor; and thereafter removing said capping oxide layer and said first oxide layer.
Claim 5
Dependent Claim
27 words
The method according to claim 1 wherein said interlevel dielectric layer is comprised of plasma-enhanced silicon oxide having a thickness of between about 6000 and 7000 Angstroms.
Claim 6
Dependent Claim
44 words
The method according to claim 1 wherein said step of implantation of nitrogen ions into said interlevel dielectric layer is completed at a dose of between about 1.0×10 13 and 5.0×10 16 ions/cm 2 at an energy of between about 25 and 100 KeV.
Claim 7
Dependent Claim
42 words
The method according to claim 1 wherein said step of annealing said interlevel dielectric layer is completed by a rapid thermal anneal process at a temperature of between about 400 and 1000 degrees C. for between about 5 seconds and 30 minutes.
Claim 8
Dependent Claim
22 words
The method according to claim 1 wherein said implanting of nitrogen atoms comprises implanting of a combination of nitrogen and oxygen atoms.
Claim 9
Independent Claim
182 words
A method of forming a polysilicon resistor in an integrated circuit comprising: providing a semiconductor substrate; providing field oxide isolation regions overlying said substrate; depositing a polysilicon layer overlying said field oxide regions and said substrate; etching said polysilicon layer where it is not covered by a mask to form a polysilicon resistor; depositing an interlevel dielectric layer overlying said polysilicon resistor; depositing a photoresist layer overlying said interlevel dielectric layer; etching said photoresist layer to form an opening wherein underlying said polysilicon resistor is completely contained within said opening; implanting nitrogen ions through said opening into said interlevel dielectric layer; removing said photoresist layer; annealing said interlevel dielectric layer to form a silicon oxynitride shield layer in said interlevel dielectric layer; etching contact openings through said interlevel dielectric layer to said polysilicon resistor; filling said contact openings with a metal layer; patterning said metal layer; covering said patterned metal layer with a passivation layer wherein said passivation layer contains hydrogen atoms and wherein said silicon oxynitride shield layer prevents hydrogen atoms from penetrating said polysilicon resistor; and completing said integrated circuit.
Claim 10
Independent Claim
182 words
A method of forming a polysilicon resistor in an integrated circuit comprising: providing a semiconductor substrate; providing field oxide isolation regions overlying said substrate; depositing a polysilicon layer overlying said field oxide regions and said substrate; etching said polysilicon layer where it is not covered by a mask to form a polysilicon resistor; depositing an interlevel dielectric layer overlying said polysilicon resistor; depositing a photoresist layer overlying said interlevel dielectric layer; etching said photoresist layer to form an opening wherein underlying said polysilicon resistor is completely contained within said opening; implanting nitrogen ions through said opening into said interlevel dielectric layer; removing said photoresist layer; annealing said interlevel dielectric layer to form a silicon oxynitride shield layer in said interlevel dielectric layer; etching contact openings through said interlevel dielectric layer to said polysilicon resistor; filling said contact openings with a metal layer; patterning said metal layer; covering said patterned metal layer with a passivation layer wherein said passivation layer contains hydrogen atoms and wherein said silicon oxynitride shield layer prevents hydrogen atoms from penetrating said polysilicon resistor; and completing said integrated circuit.
Claim 11
Dependent Claim
22 words
The method according to claim 8 wherein said polysilicon layer is formed to a thickness of between about 2000 and 4000 Angstroms.
Claim 12
Dependent Claim
112 words
The method according to claim 8 after said step of depositing said polysilicon layer further comprising: growing a first silicon dioxide layer on said polysilicon layer; implanting first ions through said first dioxide layer into said polysilicon layer to dope said polysilicon layer; depositing a capping oxide layer overlying said first oxide layer and patterning said capping oxide layer and said first oxide layer to cover planned said polysilicon resistor; implanting second ions into said polysilicon layer to provide gate doping wherein said capping oxide layer over planned said polysilicon resistor prevents said second ions from penetrating planned said resistor; and thereafter removing said capping oxide layer and said first oxide layer.
Claim 13
Dependent Claim
27 words
The method according to claim 8 wherein said interlevel dielectric layer is comprised of plasma-enhanced silicon oxide having a thickness of between about 6000 and 7000 Angstroms.
Claim 14
Dependent Claim
44 words
The method according to claim 8 wherein said step of implantation of nitrogen ions into said interlevel dielectric layer is completed at a dose of between about 1.0×10 13 and 5.0×10 16 ions/cm 2 at an energy of between about 25 and 100 KeV.
Claim 15
Dependent Claim
42 words
The method according to claim 8 wherein said step of annealing said interlevel dielectric layer is completed by a rapid thermal anneal process at a temperature of between about 400 and 1000 degrees C. for between about 5 seconds and 30 minutes.
Claim 16
Dependent Claim
22 words
The method according to claim 8 wherein said implanting of nitrogen atoms comprises implanting of a combination of nitrogen and oxygen atoms.
Claim 17
Dependent Claim
23 words
The method according to claim 8 wherein said silicon oxynitride shield is formed to a thickness of between about 500 and 2000 Angstroms.
Claim 18
Independent Claim
66 words
A method of forming a hydrogen barrier layer in an integrated circuit comprising: providing a semiconductor substrate; depositing an interlevel dielectric layer overlying said substrate; implanting nitrogen ions into said interlevel dielectric layer; annealing said interlevel dielectric layer to form a silicon oxynitride barrier layer in said interlevel dielectric layer wherein said silicon oxynitride barrier layer forms said hydrogen barrier layer; and completing said integrated circuit.
Claim 19
Independent Claim
66 words
A method of forming a hydrogen barrier layer in an integrated circuit comprising: providing a semiconductor substrate; depositing an interlevel dielectric layer overlying said substrate; implanting nitrogen ions into said interlevel dielectric layer; annealing said interlevel dielectric layer to form a silicon oxynitride barrier layer in said interlevel dielectric layer wherein said silicon oxynitride barrier layer forms said hydrogen barrier layer; and completing said integrated circuit.
Claim 20
Dependent Claim
27 words
The method according to claim 16 wherein said interlevel dielectric layer is comprised of plasma-enhanced silicon oxide having a thickness of between about 4000 and 7000 Angstroms.
Claim 21
Dependent Claim
44 words
The method according to claim 16 wherein said step of implantation of nitrogen ions into said interlevel dielectric layer is completed at a dose of between about 1.0×10 13 and 5.0×10 16 ions/cm 2 at an energy of between about 25 and 100 KeV.
Claim 22
Dependent Claim
41 words
The method according to claim 16 wherein said step of annealing said interlevel dielectric layer is completed by rapid thermal anneal process at a temperature of between about 600 and 1000 degrees C. for between about 5 seconds and 30 minutes.
Claim 23
Dependent Claim
22 words
The method according to claim 16 wherein said implanting of nitrogen atoms comprises implanting of a combination of nitrogen and oxygen atoms.
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