Frequency divider with lower power consumption

Claim 1

A frequency divider comprising: a frequency halver, supplied with an input signal having a frequency f, which generates a first intermediate signal having only a frequency f/2 from said input signal; a logic circuit supplied with a control signal indicating whether overall frequency division is selected as f/N or f/(N+1), said logic circuit emitting a switching switchover signal dependent on the selected division; an intermediate divider, supplied with said first intermediate signal from said frequency halver and with said switching signal from said logic circuit, for generating a second intermediate signal having a frequency f/8 from said first intermediate signal if division by 1/N is selected, by reducing the frequency of said first intermediate signal with a division factor of 1/4, and for generating a second intermediate signal having a frequency f/10 from said first intermediate signal if division by 1/(N+1) is selected, by reducing the frequency of said first intermediate signal with a division factor of 1/5; a divider expansion, supplied with the second intermediate signal from said intermediate divider, containing 2 N-2 divider stages including a penultimate divider stage, said penultimate divider stage emitting an output signal exhibiting jitter and having the frequency f/N or f/(N+1) dependent on said control signal, each of said divider stages in said divider expansion emitting a respective output signal, said divider expansion including jitter compensation means for reducing said jitter; and said logic circuit combining the respective output signals of the divider stages of said divider expansion with said control signal to generate said switching signal.