Clock frequency division circuit

Abstract

Abstract PURPOSE:To execute optionally even and odd number frequency division by one clock frequency dividing circuit by feeding back an output clock of a 1/2 frequency divider to other input terminal of an exclusive OR gate at odd number frequency division and giving one pulse to an n-counter. CONSTITUTION:When a signal 1 selecting odd number frequency division is inputted to an AND gate 4, an output clock of a 1/2 frequency divider 3 is fed back to other input terminal of the exclusive OR gate 1 through the AND gate 4. Then the exclusive OR gate 1 outputs a pulse with very narrow width depending on a slight time difference between the input clock and the fed-back output clock. Then one pulse is increased in one period of the output clock, resulting in obtaining an odd number of pulses. Thus, an n-counter 2 counts the pulse for each n-pulse to output the clock and the 1/2 frequency divider 3 applies 1/2 frequency division to the clock to attain odd number of frequency division.

Inventors

• 👤 Yoshiteru Imaeda
• 👤 義輝 今枝

Bibliographic Details