Semiconductor memory device capable of operating at a low power supply voltage

Abstract

Abstract A semiconductor memory device is provided which uses an externally applied power supply voltage as its operating voltage. The device comprises plural memory cells each arranged in intersections of word lines and bit lines. The device further comprises an internal power supply voltage generating circuit for receiving the externally applied power supply voltage to generate an internal power supply voltage of a first level. Furthermore, the device has a plurality of word line drivers each connected to the word lines and to a power node for receiving the internal power supply voltage. The each of the word line drivers drives a corresponding word line with the internal power supply voltage in response to a word line selection signal. According to the semiconductor memory device of the present invention, a potential on the word line becomes maintained constantly at the operating voltage even though the external power supply voltage is increased. This prevents bit lines from becoming charged more than a required level owing to an external power supply voltage variation, so that signal swing width on each bit line and a write recovery time becomes maintained constantly. As a result, there is few or no power consumption in association with an external power supply voltage variation.

Inventors

• 👤 Gong-Heum Han
• 👤 Cheol-Sung Park
• 👤 In-Cheol Shin

Bibliographic Details