Single digit line with cell contact interconnect

Claim 2

An integrated circuit memory device, comprising: a conductive digit line; a plurality of conductive tabs extending from at least one side of the conductive digit line, and a plurality of access transistors, each one of the plurality of access transistors having a first source/drain region coupled to a memory cell, a gate coupled to a word line, and a second source/drain region coupled to a node selected from the group consisting of the conductive digit line and one of the plurality of conductive tabs.

Claim 3

The integrated circuit memory device of claim 1, wherein the conductive tabs comprise material selected from the group consisting of metal and polysilicon.

Claim 4

The integrated circuit memory device of claim 1, wherein the conductive digit line comprises a conductive material selected from the group consisting of titanium, aluminum, metal and silicided polysilicon.

Claim 5

The integrated circuit memory device of claim 1, wherein the conductive tabs are formed in a direction selected from the group consisting of orthogonal to the conductive digit line and at an angle to the conductive digit line, wherein the angle is other than orthogonal.

Claim 6

The integrated circuit memory device of claim 1, wherein the conductive tabs comprise a shape selected from the group consisting of tapered, rounded and rectangular.

Claim 7

A semiconductor die, comprising: a conductive digit line; a plurality of conductive tabs extending from at least one side of the conductive digit line; and a plurality of access transistors, each one of the plurality of access transistors having a first source/drain region coupled to a memory cell, a gate coupled to a word line, and a second source/drain region coupled to a node selected from the group consisting of the conductive digit line and one of the plurality of conductive tabs.

Claim 8

A semiconductor die, comprising: a conductive digit line; a plurality of conductive tabs extending from at least one side of the conductive digit line; and a plurality of access transistors, each one of the plurality of access transistors having a first source/drain region coupled to a memory cell, a gate coupled to a word line, and a second source/drain region coupled to a node selected from the group consisting of the conductive digit line and one of the plurality of conductive tabs.

Claim 11

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 12

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 13

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region; wherein the conductive tabs comprise material selected from the group consisting of metal and polysilicon, further wherein the conductive tabs comprise a shape selected from the group consisting of tapered, rounded and rectangular, still further wherein the conductive digit line comprises a conductive material selected from the group consisting of titanium, aluminum, metal and silicided polysilicon.

Claim 14

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region; wherein the conductive tabs comprise material selected from the group consisting of metal and polysilicon, further wherein the conductive tabs comprise a shape selected from the group consisting of tapered, rounded and rectangular, still further wherein the conductive digit line comprises a conductive material selected from the group consisting of titanium, aluminum, metal and silicided polysilicon.

Claim 15

A semiconductor die, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 16

A semiconductor die, comprising: a plurality of conductive digit lines running generally in a first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 19

An integrated circuit memory device, comprising: at least one conductive digit line running generally in a first direction; and a plurality of memory cells linearly arranged in at least two columns, wherein each of the at least two columns runs generally in the first direction, further wherein at least one of the at least two columns is positioned in a spaced-apart relation in a second direction from each of the at least one conductive digit lines, still further wherein the second direction is generally orthogonal to the first direction.

Claim 20

An integrated circuit memory device, comprising: at least one conductive digit line running generally in a first direction; and a plurality of memory cells linearly arranged in at least two columns, wherein each of the at least two columns runs generally in the first direction, further wherein at least one of the at least two columns is positioned in a spaced-apart relation in a second direction from each of the at least one conductive digit lines, still further wherein the second direction is generally orthogonal to the first direction.

Claim 21

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein there is a space between adjacent ones of the plurality of conductive digit lines; and a plurality of memory cells linearly arranged in at least four columns, wherein each of the at least four columns runs generally in the first direction, further wherein at least one of the at least four columns is positioned in each space between adjacent ones of the plurality of conductive digit lines.

Claim 22

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein there is a space between adjacent ones of the plurality of conductive digit lines; and a plurality of memory cells linearly arranged in at least four columns, wherein each of the at least four columns runs generally in the first direction, further wherein at least one of the at least four columns is positioned in each space between adjacent ones of the plurality of conductive digit lines.

Claim 23

An integrated circuit memory device, comprising: a first memory array; a reference memory array; sense amplifier and bias circuitry, wherein the sense amplifier and bias circuitry is coupled between the memory arrays; and isolation circuitry coupled to the sense amplifier and bias circuitry, wherein the isolation circuitry is capable of selectively isolating each memory array from the sense amplifier and bias circuitry; wherein each memory array comprises: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines are coupled to the sense amplifier and bias circuitry through the isolation circuitry; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 24

An integrated circuit memory device, comprising: a first memory array; a reference memory array; sense amplifier and bias circuitry, wherein the sense amplifier and bias circuitry is coupled between the memory arrays; and isolation circuitry coupled to the sense amplifier and bias circuitry, wherein the isolation circuitry is capable of selectively isolating each memory array from the sense amplifier and bias circuitry; wherein each memory array comprises: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines are coupled to the sense amplifier and bias circuitry through the isolation circuitry; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of a second direction, the second direction being orthogonal to the first direction, and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region.

Claim 25

The integrated circuit memory device of claim 14, wherein the conductive tabs comprise material selected from the group consisting of metal and polysilicon.

Claim 26

The integrated circuit memory device of claim 14, wherein the conductive digit line comprises a conductive material selected from the group consisting of titanium, aluminum, metal and silicided polysilicon.

Claim 27

The integrated circuit memory device of claim 14, wherein the conductive tabs comprise a shape selected from the group consisting of tapered, rounded and rectangular.

Claim 28

An integrated circuit memory device, comprising: a plurality of active areas, wherein the plurality of active areas are linearly arranged in at least two columns running generally in a first direction and having a space between each set of adjacent columns; a field oxide region formed in the space between a set of adjacent columns; a conductive digit line running generally in the first direction, wherein the conductive digit line is formed in the field oxide region; and a plurality of conductive tabs extending from opposite sides of the conductive digit line, wherein each of the plurality of conductive tabs is coupled to one of the plurality of active areas.

Claim 29

An integrated circuit memory device, comprising: a plurality of active areas, wherein the plurality of active areas are linearly arranged in at least two columns running generally in a first direction and having a space between each set of adjacent columns; a field oxide region formed in the space between a set of adjacent columns; a conductive digit line running generally in the first direction, wherein the conductive digit line is formed in the field oxide region; and a plurality of conductive tabs extending from opposite sides of the conductive digit line, wherein each of the plurality of conductive tabs is coupled to one of the plurality of active areas.

Claim 30

An integrated circuit memory device, comprising: a plurality of active areas, wherein the plurality of active areas are linearly arranged in at least two columns running generally in a first direction and having a space between each set of adjacent columns; a field oxide region formed in the space between a set of adjacent columns, the set of adjacent columns having a first column and a second column; a conductive digit line running generally in the first direction, wherein the conductive digit line is formed above the first column; and a plurality of conductive tabs extending from one side of the conductive digit line, wherein each of the plurality of conductive tabs is coupled to one of the plurality of active areas in the second column.

Claim 31

An integrated circuit memory device, comprising: a plurality of active areas, wherein the plurality of active areas are linearly arranged in at least two columns running generally in a first direction and having a space between each set of adjacent columns; a field oxide region formed in the space between a set of adjacent columns, the set of adjacent columns having a first column and a second column; a conductive digit line running generally in the first direction, wherein the conductive digit line is formed above the first column; and a plurality of conductive tabs extending from one side of the conductive digit line, wherein each of the plurality of conductive tabs is coupled to one of the plurality of active areas in the second column.

Claim 32

An integrated circuit memory device, comprising: a field oxide region a conductive digit line; a plurality of conductive tabs extending from at least one side of the conductive digit line, wherein each of the plurality of conductive tabs extends across at least a portion of the field oxide region; and a plurality of access transistors, wherein each one of the plurality of access transistors has a first source/drain region coupled to a memory cell, a gate coupled to a word line, and a second source/drain region coupled to a node selected from the group consisting of the conductive digit line and one of the plurality of conductive tabs.

Claim 33

An integrated circuit memory device, comprising: a field oxide region a conductive digit line; a plurality of conductive tabs extending from at least one side of the conductive digit line, wherein each of the plurality of conductive tabs extends across at least a portion of the field oxide region; and a plurality of access transistors, wherein each one of the plurality of access transistors has a first source/drain region coupled to a memory cell, a gate coupled to a word line, and a second source/drain region coupled to a node selected from the group consisting of the conductive digit line and one of the plurality of conductive tabs.

Claim 34

An integrated circuit memory device, comprising: at least one conductive digit line running generally in a first direction; and a plurality of memory cells linearly arranged in at least two columns, wherein each of the at least two columns runs generally in the first direction, further wherein there are two columns of memory cells coupled to each at least one conductive digit line.

Claim 35

An integrated circuit memory device, comprising: at least one conductive digit line running generally in a first direction; and a plurality of memory cells linearly arranged in at least two columns, wherein each of the at least two columns runs generally in the first direction, further wherein there are two columns of memory cells coupled to each at least one conductive digit line.

Claim 36

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines have a first spacing between adjacent conductive digit lines in a second direction, further wherein the second direction is orthogonal to the first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of the second direction and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein the at least four columns have a second spacing between adjacent columns in the second direction, still further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region; wherein the first spacing is generally two times the second spacing.

Claim 37

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines have a first spacing between adjacent conductive digit lines in a second direction, further wherein the second direction is orthogonal to the first direction; a plurality of conductive tabs extending from at least one side of each of the plurality of conductive digit lines, wherein each of the plurality of conductive tabs runs generally in a direction selected from the group consisting of the second direction and an angled direction, the angled direction being other than orthogonal to the first direction; a plurality of memory cells linearly arranged in at least four columns, wherein each one of the at least four columns runs generally in the first direction, further wherein the at least four columns have a second spacing between adjacent columns in the second direction, still further wherein there are two adjacent columns coupled to each one of the plurality of conductive digit lines, still further wherein each one of the plurality of conductive digit lines is located in a position selected from the group consisting of between the two adjacent columns coupled to that one of the plurality of conductive digit lines and above one of the two adjacent columns coupled to that one of the plurality of conductive digit lines; and a plurality of access transistors linearly arrayed with the plurality of memory cells in the at least four columns, each one of the plurality of access transistors having a first source/drain region coupled to one of the plurality of memory cells, a gate coupled to a word line, a second source/drain region coupled to one of the plurality of conductive digit lines when that one of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region, and the second source/drain region coupled to one of the plurality of conductive tabs when none of the plurality of conductive digit lines is located above the memory cell coupled to the first source/drain region; wherein the first spacing is generally two times the second spacing.

Claim 38

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines have a first spacing between adjacent conductive digit lines in a second direction, further wherein the second direction is orthogonal to the first direction; and a plurality of memory cells linearly arranged in columns running generally in the first direction, wherein the plurality of memory cells have a second spacing between adjacent columns in the second direction, further wherein the first spacing is generally two times the second spacing.

Claim 39

An integrated circuit memory device, comprising: a plurality of conductive digit lines running generally in a first direction, wherein the plurality of conductive digit lines have a first spacing between adjacent conductive digit lines in a second direction, further wherein the second direction is orthogonal to the first direction; and a plurality of memory cells linearly arranged in columns running generally in the first direction, wherein the plurality of memory cells have a second spacing between adjacent columns in the second direction, further wherein the first spacing is generally two times the second spacing.