Patent US1959020A successfully refreshed from Google Patents.
Patent US6064739A successfully refreshed from Google Patents.
US6064739A
Expired / Lapsed
US
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System and method for copy-protecting distributed video content
Assignee: Intel Corp
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Filing: 1998-08-14
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Granted: 2000-05-16
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Expires: 2018-08-14
Abstract
Abstract A secure video content processor ("SVCP") which receives encrypted digital video information and converts it into analog information for a monitor while preventing unauthorized access to the intermediate unencrypted digital data. The SVCP uses hardware envelopes to prevent unauthorized access to the decrypted digital stream. When a need arises to transmit digital data outside the hardware envelope, the digital data is encrypted and then decrypted when it re-enters a hardware protected section of circuitry.
Inventors
- 👤 Derek L. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:10
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/70; G06F21/71; G06F21/72; G06F21/60; G06F21/606; G06F21/608; G06F21/82; G06F21/84; H; H04; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/414; H04N21/4143; H04N21/418; H04N21/4183; H04N21/43; H04N21/436; H04N21/4367; H04N21/44; H04N21/4405; H04N5/00; H04N5/76; H04N5/91; H04N5/913; H04N7/00; H04N7/16; H04N7/167; H04N7/1675; H04N2005/91357; H04N2005/91364
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
126 words
A secure video content processor having a hardware barrier, the secure video content processor comprising: a first cryptographic unit placed within the hardware barrier, the first cryptographic unit decrypting incoming digital encrypted video information and producing encrypted image frames based on the video information; a frame buffer coupled to the first cryptographic unit and placed within the hardware barrier, the frame buffer receiving the encrypted image frames from the first cryptographic unit; and a second cryptographic unit coupled to the frame buffer and placed within the hardware barrier on a single chip with the first cryptographic unit, the second cryptographic unit retrieving the encrypted image frames stored in the frame buffer, decrypting the encrypted image frames, and converting the decrypted image frames into an analog signal.
Claim 2
Dependent Claim
126 words
A secure video content processor having a hardware barrier, the secure video content processor comprising: a first cryptographic unit placed within the hardware barrier, the first cryptographic unit decrypting incoming digital encrypted video information and producing encrypted image frames based on the video information; a frame buffer coupled to the first cryptographic unit and placed within the hardware barrier, the frame buffer receiving the encrypted image frames from the first cryptographic unit; and a second cryptographic unit coupled to the frame buffer and placed within the hardware barrier on a single chip with the first cryptographic unit, the second cryptographic unit retrieving the encrypted image frames stored in the frame buffer, decrypting the encrypted image frames, and converting the decrypted image frames into an analog signal.
Claim 3
Dependent Claim
19 words
The secure video content processor of claim 1, wherein the hardware barrier is in a single semiconductor device package.
Claim 4
Dependent Claim
24 words
The secure video content processor of claim 2 wherein the first cryptographic unit sends at least one session key to the second cryptographic unit.
Claim 5
Dependent Claim
33 words
The secure video content processor of claim 1, wherein the first cryptographic unit decompresses at least one of a Joint Photographic Experts Group (JPEG) image and a Motion Photographic Experts Group (MPEG) image.
Claim 6
Dependent Claim
22 words
The secure video content processor of claim 1, wherein electronics of the first cryptographic unit are formed on a single silicon chip.
Claim 7
Dependent Claim
22 words
The secure video content processor of claim 5 wherein electronics of the second cryptographic unit are formed on a second silicon chip.
Claim 8
Dependent Claim
18 words
The system of claim 5, wherein electronics of the cryptographic unit are formed on a single silicon chip.
Claim 9
Dependent Claim
20 words
The secure video content processor of claim 1, wherein the first cryptographic unit decompresses the incoming digital encrypted video information.
Claim 10
Dependent Claim
141 words
A secure video content processor for securely processing encrypted digital video information, the secure video content processor encased in a single semiconductor package, the secure video content processor comprising: a decryption unit which receives the encrypted digital video information from a source outside of the single semiconductor package, the decryption unit decodes the encrypted digital video information to generate decrypted digital data; a processing unit coupled to the decryption unit, the processing unit configured to generate digital image frames from the decrypted digital data; a frame memory coupled to the processing unit, the frame memory retains the digital image frames generated by the processing unit; and a digital-to-analog converter coupled to the frame memory for converting the digital image frames to an analog signal, and transmitting the analog signal representing the image frames to devices located outside the single semiconductor package.
Claim 11
Dependent Claim
141 words
A secure video content processor for securely processing encrypted digital video information, the secure video content processor encased in a single semiconductor package, the secure video content processor comprising: a decryption unit which receives the encrypted digital video information from a source outside of the single semiconductor package, the decryption unit decodes the encrypted digital video information to generate decrypted digital data; a processing unit coupled to the decryption unit, the processing unit configured to generate digital image frames from the decrypted digital data; a frame memory coupled to the processing unit, the frame memory retains the digital image frames generated by the processing unit; and a digital-to-analog converter coupled to the frame memory for converting the digital image frames to an analog signal, and transmitting the analog signal representing the image frames to devices located outside the single semiconductor package.
Claim 12
Dependent Claim
17 words
The secure video content processor of claim 9 wherein the single semiconductor package is a ceramic package.
Claim 13
Dependent Claim
22 words
The secure video content processor of claim 9 wherein processor processes at least one of a JPEG image and a MPEG image.
Claim 14
Independent Claim
107 words
A system for processing video data, the system comprising: a host processor; a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package; a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package; a digital to analog converter, the digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package; and a display device designed to generate a viewable image from the analog signal.
Claim 15
Independent Claim
107 words
A system for processing video data, the system comprising: a host processor; a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package; a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package; a digital to analog converter, the digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package; and a display device designed to generate a viewable image from the analog signal.
Claim 16
Dependent Claim
15 words
The system of claim 12 further comprising a source of the encrypted digital video data.
Claim 17
Dependent Claim
15 words
The system of claim 13 further comprising a memory unit coupled to the host processor.
Claim 18
Dependent Claim
126 words
A secure video content processor comprising: a first cryptographic unit for decrypting incoming digital encrypted video information and to produce encrypted image frames based on the video information; a frame buffer coupled to the first cryptographic unit, the frame buffer for receiving the encrypted image frames from the first cryptographic unit; a second cryptographic unit coupled to the frame buffer and in communication with the first cryptographic unit to exchange a key, the second cryptographic unit for receiving the encrypted image frames stored in the fame buffer, decrypted the encrypted image frames, and converting the decrypted image frames into an analog signal; and a hardware barrier containing the first cryptographic unit, the frame buffer and the second cryptographic unit encapsulated in a single semiconductor device package.
Claim 19
Dependent Claim
126 words
A secure video content processor comprising: a first cryptographic unit for decrypting incoming digital encrypted video information and to produce encrypted image frames based on the video information; a frame buffer coupled to the first cryptographic unit, the frame buffer for receiving the encrypted image frames from the first cryptographic unit; a second cryptographic unit coupled to the frame buffer and in communication with the first cryptographic unit to exchange a key, the second cryptographic unit for receiving the encrypted image frames stored in the fame buffer, decrypted the encrypted image frames, and converting the decrypted image frames into an analog signal; and a hardware barrier containing the first cryptographic unit, the frame buffer and the second cryptographic unit encapsulated in a single semiconductor device package.
Claim 20
Dependent Claim
28 words
The secure video content processor of claim 15 wherein the key includes at least one session key transferred from the first cryptographic unit to the second cryptographic unit.
Claim 21
Dependent Claim
22 words
The secure video content processor of claim 15, wherein electronics of the first cryptographic unit are formed on a single silicon chip.
Claim 22
Dependent Claim
22 words
The secure video content processor of claim 17, wherein electronics of the second cryptographic unit are formed on a second silicon chip.
Claim 23
Dependent Claim
19 words
The secure video content processor of claim 15, wherein the second cryptographic unit includes a digital to analog converter.
Claim 24
Independent Claim
89 words
A system for processing video data, the system comprising: a host processor; a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package; a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package; and a digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package.
Claim 25
Independent Claim
89 words
A system for processing video data, the system comprising: a host processor; a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package; a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package; and a digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |