Synchronous semiconductor memory device

Claim 1

A synchronous semiconductor memory device, comprising: a memory storing data; a clock signal buffer buffering an external clock signal to generate an internal clock signal; an input buffering responsive to said internal clock signal and buffering an external control signal to generate an internal control signal; an address buffer responsive to said internal clock signal and buffering an external address signal to generate an internal address signal; a mode register in which operation mode can be set designating a reading procedure of said data from said memory and a writing procedure of external data into said memory; a data reading circuit reading said data stored in said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a read signal; a data writing circuit writing external data into said memory in response to said operation mode set in said mode register and in response to said internal clock signal and a write signal; a command decoder generating a mode set signal for setting said operation mode in said mode register in response to said internal control signal and generating said read signal and said write signal; and a non-volatile memory storing said mode set signal and said internal address signal and supplying said stored mode set signal and said stored internal address signal to said mode register.