Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced

Claim 2

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising: clock buffer means for generating a first internal clock signal in accordance with said external clock signal; latch means for taking in an externally applied external clock enable signal designating validity of said external clock signal in synchronization with said first internal clock signal, and for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active; clock enable means for delaying said input buffer enable signal for generating an internal clock enable signal; internal clock generating means activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal; input buffer means activated in response to said input buffer enable signal being active for buffering an externally applied signal different from said external clock enable signal and said external clock signal, said input buffer means using voltages on first and second power supply nodes as operational power supply voltages and including means for shutting off a current flowing path between said first and second power supply nodes when said input buffer enable signal is inactive; and internal signal generating means for latching an output signal from said input buffer means in synchronization with said second internal clock signal for generating an internal signal.

Claim 3

The synchronous semiconductor memory device according to claim 1, wherein said external clock signal repetitively changes between first and second potential levels; said latch means includes means for latching said external clock enable signal in synchronization with the change in potential level of said first internal clock signal from said first potential level to said second potential level for outputting; and said internal signal generating means has substantially a same common structure as said latch means, and latches an output signal from said input buffer means in response to the change of said second internal clock signal from said first potential level to said second potential level for generating said internal signal.

Claim 4

The synchronous semiconductor memory device according to claim 1, wherein said latch means includes a buffer circuit for buffering said external clock enable signal, a first latch coupled to receive an output signal from said buffer circuit, set to a through state permitting passage of an output signal from said buffer circuit in response to said first internal clock signal being at said second potential level and set to a latch state for maintaining a state of the output signal regardless of a signal applied from said buffer circuit in response to said first internal clock signal being at said first potential level, a second latch coupled to said first latch, set to said latch state in response to said first internal clock signal being at said first potential level and set to said through state in response to said first internal clock signal being at said second potential level.

Claim 5

The synchronous semiconductor memory device according to claim 1, wherein said clock enable means includes a latch circuit which is set to the latch state complementarily to said latch means in synchronization with said first internal clock signal.

Claim 6

The synchronous semiconductor memory device according to claim 1, wherein said clock buffer means includes a buffer circuit for buffering said external clock signal, and means for generating a signal changing in synchronization with change of an output signal from said buffer circuit as said first internal clock signal.

Claim 7

The semiconductor memory device according to claim 5, further comprising a delay circuit for delaying an output signal from said buffer circuit for application to the first internal clock signal generating means.

Claim 8

The synchronous semiconductor memory device according to claim 3, wherein said latch means includes a delay circuit provided between said buffer circuit and said first latch.

Claim 9

The synchronous semiconductor memory device according to claim 1, further comprising a delay circuit provided between said input buffer means and said internal signal generating means.

Claim 10

The synchronous semiconductor memory device according to claim 1, wherein said clock buffer means includes a buffer circuit for buffering said external clock signal, and a pulse generator coupled to receive an output signal of said buffer circuit, for generating a one-shot pulse signal as said first internal clock signal in response to the output signal of said buffer circuit.

Claim 11

The synchronous semiconductor memory device according to claim 1, wherein said clock buffer includes a buffer for buffering said external clock signal, and a gate for gating an output of said buffer to generate said first internal clock signal, and said internal clock generating means includes another gate enabled in response to said internal clock enable signal for gating said output signal of said buffer to generate said internal clock signal, said gate and said another gate providing substantially a same common gate delay.

Claim 12

The synchronous semiconductor memory device according to claim 1, wherein said input buffer means includes a current-mirror type differential amplifier for differentially amplifying the externally applied signal and a reference potential for application to said internal signal generating means.

Claim 13

The synchronous semiconductor memory device according to claim 11, wherein said current-mirror type differential amplifier further includes an element responsive to deactivation of said internal clock enable signal for coupling an output of said current-mirror type differential amplifier to said second power supply node.

Claim 14

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising: clock buffer means for generating a first internal clock signal in accordance with said external clock signal; latch means for taking in an externally applied external clock enable signal designating validity of said external clock signal in synchronization with said first internal clock signal, and for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active; clock enable means for delaying said input buffer enable signal for generating an internal clock enable signal; internal clock generating means activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal; internal signal generating means for latching a received signal in synchronization with said second internal clock signal for generating an internal signal.

Claim 15

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising: clock buffer means for generating a first internal clock signal in accordance with said external clock signal; latch means for taking in an externally applied external clock enable signal designating validity of said external clock signal in synchronization with said first internal clock signal, and for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active; clock enable means for delaying said input buffer enable signal for generating an internal clock enable signal; internal clock generating means activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal; internal signal generating means for latching a received signal in synchronization with said second internal clock signal for generating an internal signal.

Claim 16

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising: clock buffer circuitry for generating a first internal clock signal in accordance with said external clock signal; a buffer circuit for buffering an externally applied external clock enable signal designating validity of said first internal clock signal; a first latch coupled to receive an output signal from said buffer circuit, set to a through state permitting passage of the output signal from said buffer circuit in response to said first internal clock signal being at a first potential level and set to a latch state for maintaining an output signal thereof regardless of the state of the output signal from said buffer circuit in response to said first internal clock signal being at a second potential level; a second latch coupled to said first latch, set to said latch state in response to said first internal clock signal being at said first potential level and set to said through state in response to said first internal clock signal being at said second potential level, for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active; a latch circuit coupled to said second latch and set to the latch state complementarily to said second latch in synchronization with said first internal clock signal, for delaying said input buffer enable signal to generate an internal clock enable signal; internal clock generating circuitry activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal; and an input buffer means for buffering an externally applied signal different from said external clock enable signal and said external clock signal to generate a pre-internal signal when activated in response to said input buffer enable signal being active, said input buffer means including means for shutting off a current flowing through the input buffer means to inactivate the buffering operation in response to said input buffer enable signal being inactive.

Claim 17

A synchronous semiconductor memory device operating in synchronization with an externally applied external clock signal, comprising: clock buffer circuitry for generating a first internal clock signal in accordance with said external clock signal; a buffer circuit for buffering an externally applied external clock enable signal designating validity of said first internal clock signal; a first latch coupled to receive an output signal from said buffer circuit, set to a through state permitting passage of the output signal from said buffer circuit in response to said first internal clock signal being at a first potential level and set to a latch state for maintaining an output signal thereof regardless of the state of the output signal from said buffer circuit in response to said first internal clock signal being at a second potential level; a second latch coupled to said first latch, set to said latch state in response to said first internal clock signal being at said first potential level and set to said through state in response to said first internal clock signal being at said second potential level, for generating and outputting an input buffer enable signal which is activated when said external clock enable signal is active; a latch circuit coupled to said second latch and set to the latch state complementarily to said second latch in synchronization with said first internal clock signal, for delaying said input buffer enable signal to generate an internal clock enable signal; internal clock generating circuitry activated in response to said internal clock enable signal being active, for generating a second internal clock signal in accordance with said external clock signal; and an input buffer means for buffering an externally applied signal different from said external clock enable signal and said external clock signal to generate a pre-internal signal when activated in response to said input buffer enable signal being active, said input buffer means including means for shutting off a current flowing through the input buffer means to inactivate the buffering operation in response to said input buffer enable signal being inactive.

Claim 18

The synchronous semiconductor memory device according to claim 14, further comprising internal signal generating circuitry for latching said pre-internal signal from the input buffer means in synchronization with said second internal clock signal for generating an internal signal.

Claim 19

The synchronous semiconductor memory device according to claim 14, wherein said input buffer means includes a current mirror type differential amplifying stage for differentially amplifying said externally applied signal and a reference potential, and a current source coupled to the differential amplifying state and cutting off a current flowing through the differential amplifying stage when inactivated in response to said input buffer enable signal being inactive.