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Patent US6064248A successfully refreshed from Google Patents.
US6064248A
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US
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Clock pulse transmission circuit
Assignee: Advantest Corp
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Filing: 1998-05-07
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Granted: 2000-05-16
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Expires: 2018-05-07
Abstract
Abstract A clock pulse transmission circuit is provided which can automatically correct, in case the duty factor of transmitted clock pulses has an error, the duty factor error. In a receiving unit 2, a pair of positive and negative clock pulses Sp and Sn transmitted from a transmitting unit 1 are inputted to a receiver 12 which outputs, in response thereto, a pair of positive and negative clock pulses V3 and V4. The DC components of these positive and negative clock pulses are taken out by a first integrator circuit and a second integrator circuit respectively to transmit them to the transmitting unit 1 through a pair of transmission lines 25 and 26, respectively. In the transmitting unit 1, a difference between the direct current levels of the respective positive and negative clock pulses is found and integrated. The integrated value is supplied to a driver 6 as a threshold voltage Vth. The driver 6 compares an output signal of a time constant circuit 20 with the threshold voltage to output a pair of positive and negative clock pulses Sp and Sn and transmits them to the receiving unit 2.
Inventors
- 👤 Nobusuke Seki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:18
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/08; H04L25/085
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
329 words
A clock pulse transmission circuit including a transmitting unit for outputting a first pair of positive and negative clock pulses to transmit them, a receiving unit for receiving said first pair of positive and negative clock pulses transmitted from said transmitting unit and outputting a second pair of positive and negative clock pulses, and signal transmission paths for connecting between said transmitting unit and said receiving unit, and wherein said receiving unit comprises: receiver means for outputting the second pair of positive and negative clock pulses in response to clock pulses transmitted from said transmitting unit through said signal transmission paths and supplied to input terminals of said receiver means; first and second filter means for taking out direct current (DC) components of the second pair of positive and negative clock pulses outputted from said receiver means, respectively; and a first buffer circuit and a second buffer circuit for transmitting respective output signals of said first and second filter means to said transmitting unit through a pair of control signal transmission paths; and wherein said transmitting unit comprises: a time constant circuit for outputting a clock signal having sloping leading edges and sloping trailing edges; a driver for comparing the output clock signal of said time constant circuit with a threshold voltage, outputting the first pair of positive and negative clock pulses corresponding to a difference between the output clock signal of said time constant circuit and the threshold voltage, and transmitting the first pair of positive and negative clock pulses to said receiving unit; differential amplifier means for finding a difference between output signals respectively transmitted from said first and second buffer circuits in said receiving unit to detect an error in duty factory of said second pair of positive and negative clock pulses outputted from said receiver means in said receiving unit; and integrator means for integrating an output signal of said differential amplifier means to supply an integrated value to said driver as the threshold voltage.
Claim 2
Dependent Claim
329 words
A clock pulse transmission circuit including a transmitting unit for outputting a first pair of positive and negative clock pulses to transmit them, a receiving unit for receiving said first pair of positive and negative clock pulses transmitted from said transmitting unit and outputting a second pair of positive and negative clock pulses, and signal transmission paths for connecting between said transmitting unit and said receiving unit, and wherein said receiving unit comprises: receiver means for outputting the second pair of positive and negative clock pulses in response to clock pulses transmitted from said transmitting unit through said signal transmission paths and supplied to input terminals of said receiver means; first and second filter means for taking out direct current (DC) components of the second pair of positive and negative clock pulses outputted from said receiver means, respectively; and a first buffer circuit and a second buffer circuit for transmitting respective output signals of said first and second filter means to said transmitting unit through a pair of control signal transmission paths; and wherein said transmitting unit comprises: a time constant circuit for outputting a clock signal having sloping leading edges and sloping trailing edges; a driver for comparing the output clock signal of said time constant circuit with a threshold voltage, outputting the first pair of positive and negative clock pulses corresponding to a difference between the output clock signal of said time constant circuit and the threshold voltage, and transmitting the first pair of positive and negative clock pulses to said receiving unit; differential amplifier means for finding a difference between output signals respectively transmitted from said first and second buffer circuits in said receiving unit to detect an error in duty factory of said second pair of positive and negative clock pulses outputted from said receiver means in said receiving unit; and integrator means for integrating an output signal of said differential amplifier means to supply an integrated value to said driver as the threshold voltage.
Claim 3
Dependent Claim
163 words
The clock pulse transmission circuit according to claim 1, wherein said driver in said transmitting unit is constituted by a differential buffer which generates said first pair of positive and negative clock pulses in response to the output clock signal of said time constant circuit supplied to one input terminal thereof and the threshold voltage of said integrator means supplied to the other input terminal thereof; said receiver means in said receiving unit is also constituted by a differential buffer which outputs said second pair of positive and negative clock pulses in response to the first pair of positive and negative clock pulses transmitted from said driver in said transmitting unit supplied to two input terminals thereof, respectively; and said first and second filter means in said receiving unit are a first integrator circuit and a second integrator circuit respectively for integrating the positive and negative clock pulses of the second pair to detect mean voltage values of their respective direct current components.
Claim 4
Dependent Claim
44 words
The clock pulse transmission circuit according to claim 1, wherein a third buffer circuit and a fourth buffer circuit are inserted respectively between the two input terminals of said differential amplifier means in said transmitting unit and said pair of control signal transmission paths.
Claim 5
Dependent Claim
26 words
The clock pulse transmission circuit according to claim 1, wherein another buffer circuit is inserted between said integrator means and said driver in said transmitting unit.
Claim 6
Dependent Claim
36 words
The clock pulse transmission circuit according to claim 1, wherein said driver in said transmitting unit and said receiver means in said receiving unit are each constituted by a respective differential buffer using an emitter-coupled logic.
Claim 7
Dependent Claim
309 words
A clock pulse transmission circuit including a transmitting unit for outputting a first pair of positive and negative clock pulses to transmit them, a receiving unit for receiving said first pair of positive and negative clock pulses transmitted from said transmitting unit and outputting a second pair of positive and negative clock pulses, and signal transmission paths for connecting between said transmitting unit and said receiving unit, and wherein said receiving unit comprises: receiver means for outputting clock pulses in response to the first pair of positive and negative clock pulses transmitted from said transmitting unit through said signal transmission paths and supplied to input terminals of said receiver means; a time constant circuit for giving a slope to the leading edge and the trailing edge of each of the clock pulses outputted from said receiver means to supply an output clock signal; a differential buffer for comparing the output clock signal of said time constant circuit with a threshold voltage to output the second pair of positive and negative clock pulses corresponding to a difference between the output clock signal and the threshold voltage; first and second filter means for taking out direct current (DC) components of said second pair of positive and negative clock pulses outputted from said differential buffer, respectively; differential amplifier means for finding a difference between the signals respectively outputted from said first and second filter means to detect an error in duty factor of said second pair of positive and negative clock pulses outputted from said differential buffer; and integrator means for integrating an output signal of said differential amplifier means to supply an integrated value to said differential buffer as the threshold voltage; and wherein said transmitting unit comprises: a driver for outputting the first pair of positive and negative clock pulses in response to clock pulses supplied to its input terminal.
Claim 8
Dependent Claim
309 words
A clock pulse transmission circuit including a transmitting unit for outputting a first pair of positive and negative clock pulses to transmit them, a receiving unit for receiving said first pair of positive and negative clock pulses transmitted from said transmitting unit and outputting a second pair of positive and negative clock pulses, and signal transmission paths for connecting between said transmitting unit and said receiving unit, and wherein said receiving unit comprises: receiver means for outputting clock pulses in response to the first pair of positive and negative clock pulses transmitted from said transmitting unit through said signal transmission paths and supplied to input terminals of said receiver means; a time constant circuit for giving a slope to the leading edge and the trailing edge of each of the clock pulses outputted from said receiver means to supply an output clock signal; a differential buffer for comparing the output clock signal of said time constant circuit with a threshold voltage to output the second pair of positive and negative clock pulses corresponding to a difference between the output clock signal and the threshold voltage; first and second filter means for taking out direct current (DC) components of said second pair of positive and negative clock pulses outputted from said differential buffer, respectively; differential amplifier means for finding a difference between the signals respectively outputted from said first and second filter means to detect an error in duty factor of said second pair of positive and negative clock pulses outputted from said differential buffer; and integrator means for integrating an output signal of said differential amplifier means to supply an integrated value to said differential buffer as the threshold voltage; and wherein said transmitting unit comprises: a driver for outputting the first pair of positive and negative clock pulses in response to clock pulses supplied to its input terminal.
Claim 9
Dependent Claim
43 words
The clock pulse transmission circuit according to claim 6, wherein a first buffer circuit and a second buffer circuit are inserted respectively between said first and second filter means and the two input terminals of said differential amplifier means in said receiving unit.
Claim 10
Dependent Claim
27 words
The clock pulse transmission circuit according to claim 6, wherein a buffer circuit is inserted between said integrator means and said differential buffer in said receiving unit.
Claim 11
Dependent Claim
40 words
The clock pulse transmission circuit according to claim 6, wherein said driver in said transmitting unit, and said receiver means and said differential buffer in said receiving unit are each constituted by a respective differential buffer using an emitter-coupled logic.
References Cited (Backward Citations)
US4694504A
Cited
US4713841A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |