← Back to Patent Explorer
US6064113A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances

Assignee: Bell Semiconductor LLC
•
Filing: 1998-01-13
•
Granted: 2000-05-16
•
Expires: 2018-01-13
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor device package is presented for housing an integrated circuit which includes bonding fingers located within a conductive ring structure and routed to device terminals on an underside surface of the semiconductor device package. The semiconductor device package includes a die area defined upon a planar upper surface, a conductive ring surrounding the die area, and a first set of bonding fingers arranged within the conductive ring. The die area is dimensioned to receive the integrated circuit. The conductive ring may be a power ring or a ground ring. The conductive ring and the first set of bonding fingers are located within a first signal layer adjacent to the upper surface. A set of bonding pads which serve as device terminals reside within a second signal layer adjacent to a planar underside surface. The semiconductor device package also includes a first set of signal traces connected to bonding fingers within the first signal layer, a second set of signal traces connected to bonding pads within the second signal layer, and vias connecting members of the first and second sets of signal traces. The signal traces and vias form signal paths between members of the first set of bonding fingers and corresponding bonding pads which "loop back" upon themselves. The semiconductor device package also includes a combined power and ground plane configured to stabilize the impedances of the "loop back" signal paths.

Inventors

  • 👤 Scott L. Kirkman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 14:03
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/63; H10W70/635; H10W70/654; H10W70/655; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 170 words
A semiconductor device package for housing an integrated circuit and having planar opposed upper and underside surfaces, the semiconductor device package comprising: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ring surrounding the die area; a first set of bonding fingers arranged between the conductive ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads.
Claim 2
Dependent Claim 170 words
A semiconductor device package for housing an integrated circuit and having planar opposed upper and underside surfaces, the semiconductor device package comprising: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ring surrounding the die area; a first set of bonding fingers arranged between the conductive ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads.
Claim 3
Dependent Claim 134 words
The semiconductor device package as recited in claim 1, further comprising: a continuous electrically conductive ground plane adapted for coupling to an electrical ground potential and positioned between the first and second signal layers; and a combined power and ground plane positioned between the ground plane and the second signal layer, comprising: a power portion adapted for coupling to a source of electrical power; and a ground portion adapted for coupling to the electrical ground potential; wherein the ground portion of the combined power and ground plane includes regions adjacent to members of the second set of signal traces within the second signal layer such that the impedances of the signal paths formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads remain substantially uniform.
Claim 4
Dependent Claim 22 words
The semiconductor device package as recited in claim 1, wherein the conductive ring is adapted for coupling to an electrical ground potential.
Claim 5
Dependent Claim 23 words
The semiconductor device package as recited in claim 1, wherein the conductive ring is adapted for coupling to a source of electrical power.
Claim 6
Dependent Claim 26 words
The semiconductor device package as recited in claim 1, wherein the bonding pads are coated with solder and function as terminals of the semiconductor device package.
Claim 7
Dependent Claim 88 words
The semiconductor device package as recited in claim 1, further comprising: a second set of bonding fingers within the first signal layer and arranged outside of the conductive ring; a third set of signal traces within the first signal layer, wherein members of the third set of signal traces are connected to corresponding members of the second set of bonding fingers; and a second set of vias connecting members of the third set of signal traces to corresponding members of the bonding pads within the second signal layer.
Claim 8
Dependent Claim 181 words
A semiconductor device package for housing an integrated circuit and having planar opposed upper and underside surfaces, the semiconductor device package comprising: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ground ring surrounding the die area; a continuous electrically conductive power ring surrounding the ground ring; a first set of bonding fingers arranged between the ground ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads.
Claim 9
Dependent Claim 181 words
A semiconductor device package for housing an integrated circuit and having planar opposed upper and underside surfaces, the semiconductor device package comprising: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ground ring surrounding the die area; a continuous electrically conductive power ring surrounding the ground ring; a first set of bonding fingers arranged between the ground ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads.
Claim 10
Dependent Claim 134 words
The semiconductor device package as recited in claim 7, further comprising: a continuous electrically conductive ground plane adapted for coupling to an electrical ground potential and positioned between the first and second signal layers; and a combined power and ground plane positioned between the ground plane and the second signal layer, comprising: a power portion adapted for coupling to a source of electrical power; and a ground portion adapted for coupling to the electrical ground potential; wherein the ground portion of the combined power and ground plane includes regions adjacent to members of the second set of signal traces within the second signal layer such that the impedances of the signal paths formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads remain substantially uniform.
Claim 11
Dependent Claim 37 words
The semiconductor device package as recited in claim 7, wherein the ground ring is adapted for coupling to an electrical ground potential, and wherein the power ring is adapted for coupling to a source of electrical power.
Claim 12
Dependent Claim 88 words
The semiconductor device package as recited in claim 7, further comprising: a second set of bonding fingers within the first signal layer and arranged outside of the conductive ring; a third set of signal traces within the first signal layer, wherein members of the third set of signal traces are connected to corresponding members of the second set of bonding fingers; and a second set of vias connecting members of the third set of signal traces to corresponding members of the bonding pads within the second signal layer.
Claim 13
Dependent Claim 209 words
An assembly, comprising: an integrated circuit having a plurality of input/output (I/O) pads arranged upon an upper surface; a substrate having opposed planar upper and underside surfaces, wherein the substrate comprises: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ring surrounding the die area; a first set of bonding fingers arranged between the conductive ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads; and a set of bonding wires connecting members of the plurality I/O pads of the integrated circuit to corresponding members of the first set of bonding fingers of the substrate.
Claim 14
Dependent Claim 209 words
An assembly, comprising: an integrated circuit having a plurality of input/output (I/O) pads arranged upon an upper surface; a substrate having opposed planar upper and underside surfaces, wherein the substrate comprises: a die area defined upon the upper surface and dimensioned to receive the integrated circuit; a first signal layer adjacent to the upper surface, comprising: a continuous electrically conductive ring surrounding the die area; a first set of bonding fingers arranged between the conductive ring and the die area; and a first set of signal traces connected to corresponding members of the first set of bonding fingers; a second signal layer adjacent to the underside surface, comprising: a set of bonding pads; and a second set of signal traces connected to corresponding members of the set of bonding pads; and a first set of vias connecting members of the first set of signal traces to corresponding members of the second set of signal traces such that signal paths are formed between members of the first set of bonding fingers and corresponding members of the set of bonding pads; and a set of bonding wires connecting members of the plurality I/O pads of the integrated circuit to corresponding members of the first set of bonding fingers of the substrate.
Claim 15
Dependent Claim 23 words
The assembly as recited in claim 11, wherein the integrated circuit comprises at least one electronic device formed upon a monolithic semiconductor substrate.
Claim 16
Dependent Claim 15 words
The assembly as recited in claim 11, wherein the substrate comprises a fiberglass-epoxy composite material.
Claim 17
Dependent Claim 14 words
The assembly as recited in claim 11, wherein the substrate comprises a ceramic material.
Claim 18
Dependent Claim 20 words
The assembly as recited in claim 11, wherein the conductive ring is adapted for coupling to an electrical ground potential.
Claim 19
Dependent Claim 21 words
The assembly as recited in claim 11, wherein the conductive ring is adapted for coupling to a source of electrical power.

References Cited (Backward Citations)

US5545923A Cited
US5686699A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-05-16 2003-11-15 2004-05-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-05-16 2007-11-15 2008-05-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-05-16 2011-11-15 2012-05-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag