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US6060928A
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Device for delaying clock signal
Assignee: SK Hynix Inc
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Filing: 1998-07-30
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Granted: 2000-05-09
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Expires: 2018-07-30
Abstract
Abstract Device for delaying a clock signal using a ring delay is disclosed. The device can include a delay for delaying an external clock signal eCLK as much as time delays d1+d2 of a time delay d1 occurring on reception and a time delay d2 occurring on driving an output buffer, a pulse generator for receiving the clock signal from the delay and generating rectangular pulses synchronous to rising edges, and a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signal generated in the pulse generator as well as latching a signal from each unit delay synchronous to the clock signal rCLK received in the chip. The first clock signal delay is for delaying the clock signal rCLK in a course corresponding to a number of circulation, and a second clock signal delay is for making a fine delay of the clock signal from the first clock signal delay in response to a latch signal from the ring delay. A reset signal generator is for resetting the ring delay and the first, and second clock signal delays in response to the clock signal rCLK.
Inventors
- 👤 Young Hyun Jun
- 👤 Hoi Jun Yoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:10
CPC Classifications
H; H03; H03K; H03K5/00; G; G11; G11C; G11C7/00; G11C7/22; G11C7/222
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A device for delaying a clock signal comprising: a delay for delaying an external clock signal eCLK up to a delay d1+d2, wherein the delay d1 is a natural delay incurred on reception and the delay d2 is a natural delay incurred on driving an output buffer; a pulse generator for receiving a clock signal from the delay and generating pulse signals synchronous to rising edges; a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signals generated in the pulse generator as well as latching a signal from each unit delay synchronous to a clock signal rCLK received in the device wherein the clock signal rCLK is derived from the external clock signal eCLK plus the delay d1; a first clock signal delay for making a course delay of the clock signal rCLK corresponding to a number of circulation; a second clock signal delay for making a fine delay of the clock signal rCLK delayed by the course delay from the first clock signal delay in response to a latch signal from the ring delay; and, a reset signal generator for resetting the ring delay and the first, and second clock signal delays in response to the clock signal rCLK.
Claim 2
Independent Claim
211 words
A device for delaying a clock signal comprising: a delay for delaying an external clock signal eCLK up to a delay d1+d2, wherein the delay d1 is a natural delay incurred on reception and the delay d2 is a natural delay incurred on driving an output buffer; a pulse generator for receiving a clock signal from the delay and generating pulse signals synchronous to rising edges; a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signals generated in the pulse generator as well as latching a signal from each unit delay synchronous to a clock signal rCLK received in the device wherein the clock signal rCLK is derived from the external clock signal eCLK plus the delay d1; a first clock signal delay for making a course delay of the clock signal rCLK corresponding to a number of circulation; a second clock signal delay for making a fine delay of the clock signal rCLK delayed by the course delay from the first clock signal delay in response to a latch signal from the ring delay; and, a reset signal generator for resetting the ring delay and the first, and second clock signal delays in response to the clock signal rCLK.
Claim 3
Dependent Claim
105 words
A device for delaying a clock signal as claimed in claim 1, wherein the first clock signal delay includes; a course delay having a plurality of course delay units CDU, each course delay unit delaying the clock signal rCLK by a fixed delay, a first switching part for switching respective outputs of the course delay units CDU in the course delay, and a course delay controller for controlling the first switching part so as to count the number of circulation of the pulse signals from the pulse generator in the ring delay for making the course delay for a time period corresponding to the number.
Claim 4
Dependent Claim
106 words
A device for delaying a clock signal as claimed in claim 1, wherein the second clock signal delay includes; a fine delay having a number of fine delay units FDUs for making fine delay of the delayed clock signal rCLK from the first clock signal delay, a second switching part for respectively switching outputs of the fine delay units FDUs in the fine delay, and a fine delay controller for controlling the second switching part for making the fine delay of the delayed clock signal rCLK received from the first clock signal delay for a time period corresponding to each latch signal from the ring delay.
Claim 5
Dependent Claim
88 words
A device for delaying a clock signal as claimed in claim 1, wherein the ring delay includes, the plurality of unit delays connected in series between a first unit delay and a last unit delay in the plurality of unit delays, wherein the last unit delay is further connected in series to the first unit delay for circulating and delaying the pulse signals generated in the pulse generator, and a plurality of latches each for latching a signal from each unit delay synchronous to the clock signal rCLK.
Claim 6
Dependent Claim
19 words
A device for delaying a clock signal as claimed in claim 4, wherein the plurality of latches includes flipflops.
Claim 7
Dependent Claim
52 words
A device for delaying a clock signal as claimed in claim 1, wherein the ring delay provides a signal corresponding to one circulation of the pulse signals to the first clock signal delay every time the pulse signals make one circulation and provides all latched signals to the second clock signal delay.
References Cited (Backward Citations)
US5534809A
Cited
US5526393A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |