Dual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfaces

Claim 2

A computer system having a core logic chipset configurable as either an accelerated graphics port (AGP) interface or a Fibre Channel Arbitrated Loop (FC-AL) interface and connects a computer processor and memory thereto, said system comprising: a central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chipset connected to the host bus and the random access memory bus; said core logic chipset comprising; an accelerated graphics port (AGP) request queue; an AGP reply queue; an AGP data and control logic; an arbiter; an FC-AL request queue; an FC-AL reply queue; an FC-AL control register; an FC-AL data direct memory access register; a PCI to PCI bridge; said AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic connected to said random access memory bus; said AGP data and control logic connected to said AGP request and reply queues; said AGP data and control logic connected to an AGP interface; said arbiter connection to said AGP interface; said AGP request and reply queues connected to a host bus interface, said host bus interface connected to said host bus; a host to PCI bus bridge connected to said host bus interface and connected to a primary PCI bus; said PCI to PCI bridge connected to said AGP interface, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to primary PCI bus bridge and said AGP data and control logic; said FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said FC-AL control register connected to said FC-AL request and reply queues; an FC-AL data direct memory access register connected to said FC-AL control register; and said arbiter, said FC-AL data direct memory access register and said FC-AL control register connected to an FC-AL interface, wherein said core logic chipset configured as an interface bridge between the host bus and said AGP interface if a first configuration signal is present, or as an interface bridge between the host bus and said FC-AL interface if a second configuration signal is present; and said core logic chipset configured as an interface bridge between the random access memory bus and said AGP interface if the first configuration signal is present, or as an interface bridge between the random access memory bus and said FC-AL interface if the second configuration signal is present.

Claim 3

The computer system of claim 1, wherein the central processing unit is a plurality of central processing units.

Claim 4

The computer system of claim 1, wherein the core logic chipset is at least one integrated circuit.

Claim 5

The computer system of claim 3, wherein the at least one integrated circuit core logic chipset is at least one application specific integrated circuit.

Claim 6

The computer system of claim 3, wherein the at least one integrated circuit core logic chipset is at least one programnmnable logic array integrated circuit.

Claim 7

The computer system of claim 3, further comprising a signal switch which connects said AGP interface, if the first configuration signal is present, or connects said FC-AL interface, if the second configuration signal is present, to external connections on the at least one integrated circuit.

Claim 8

The computer system of claim 1, further comprising an FC-AL logic circuit for transmitting and receiving high speed digital serial information, said FC-AL logic circuit connected to the FC-AL interface of the core logic chipset.

Claim 9

The computer system of claim 7, further comprising an FC-AL physical link module connected to said FC-AL logic circuit and used as a signal interface between said FC-AL logic circuit and an FC-AL network.

Claim 10

The computer system of claim 8, wherein said FC-AL physical link module comprises emitter coupled logic drivers and receivers.

Claim 11

The computer system of claim 8, wherein said FC-AL physical link module comprises laser light drivers and laser photo optic light receivers.

Claim 12

The computer system of claim 8, wherein said FC-AL physical link module comprises light emitting diode drivers and photo optic light receivers.

Claim 13

The computer system of claim 1, wherein the host bus, random access memory bus, and an AGP bus connected to said AGP interface are on a printed circuit board.

Claim 14

The computer system of claim 12, further comprising an FC-AL logic circuit and an FC-AL physical link module on said printed circuit board.

Claim 15

The computer system of claim 1, wherein the first and second configuration signals are from an electrical signal sent from a hardwired jumper circuit located on the printed circuit board.

Claim 16

The computer system of claim 1, wherein the first and second configuration signals are from software control of said core logic chipset.

Claim 17

The computer system of claim 15, wherein the first configuration signal is from detection of an AGP device on the AGP bus connected to the first AGP interface.

Claim 18

The computer system of claim 16, wherein the first or second configuration signal is determined during power on self test of the computer system.

Claim 19

The computer system of claim 16, wherein the first or second configuration signal is determined during configuration of the computer system.

Claim 20

A core logic chipset configurable for either an accelerated graphics port (AGP) interface or a Fibre Channel Arbitrated Loop (FC-AL) interface, comprising: an accelerated graphics port (AGP) request queue; an AGP reply queue; an AGP data and control logic; an arbiter; an FC-AL request queue; an FC-AL reply queue; an FC-AL control register; an FC-AL data direct memory access register; a PCI to PCI bridge; said AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic adapted for connection to a computer system random access memory; said AGP data and control logic connected to said AGP request and reply queues; said AGP data and control logic adapted for connection to an AGP interface; said arbiter adapted for connection to the AGP interface; said AGP request and reply queues connected to a host bus interface, said host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto; a host to PCI bus bridge connected to said host bus interface and adapted for connection to a computer system primary PCI bus; said PCI to PCI bridge connected to said AGP interface, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to primary PCI bus bridge and said AGP data and control logic; said FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said FC-AL control register connected to said FC-AL request and reply queues; an FC-AL data direct memory access register connected to said FC-AL control register; and said arbiter, said FC-AL data direct memory access register and said FC-AL control register adapted for connection to an FC-AL logic circuit.

Claim 21

A core logic chipset configurable for either an accelerated graphics port (AGP) interface or a Fibre Channel Arbitrated Loop (FC-AL) interface, comprising: an accelerated graphics port (AGP) request queue; an AGP reply queue; an AGP data and control logic; an arbiter; an FC-AL request queue; an FC-AL reply queue; an FC-AL control register; an FC-AL data direct memory access register; a PCI to PCI bridge; said AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic adapted for connection to a computer system random access memory; said AGP data and control logic connected to said AGP request and reply queues; said AGP data and control logic adapted for connection to an AGP interface; said arbiter adapted for connection to the AGP interface; said AGP request and reply queues connected to a host bus interface, said host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto; a host to PCI bus bridge connected to said host bus interface and adapted for connection to a computer system primary PCI bus; said PCI to PCI bridge connected to said AGP interface, wherein said PCI to PCI bridge transfers PCI information transactions between said Host to primary PCI bus bridge and said AGP data and control logic; said FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said FC-AL control register connected to said FC-AL request and reply queues; an FC-AL data direct memory access register connected to said FC-AL control register; and said arbiter, said FC-AL data direct memory access register and said FC-AL control register adapted for connection to an FC-AL logic circuit.

Claim 22

The core logic chipset according to claim 19, further comprising a signal switch between the AGP interface and the FC-AL interface, and a common AGP/FC-AL bus.

Claim 23

The core logic chipset according to claim 20, wherein said signal switch is controlled by a hardware jumper applying a control signal to said core logic chipset.

Claim 24

The core logic chipset according to claim 20, wherein said signal switch is controlled by software configuring a control register in said core logic chipset.

Claim 25

A core logic chipset configurable for two accelerated graphics port (AGP) interfaces, an AGP interface and a Fibre Channel Arbitrated Loop (FC-AL) interface, or two FC-AL interfaces, comprising: first and second accelerated graphics port (AGP) request queues; first and second AGP reply queues; first and second AGP data and control logic; first and second arbiters; first and second FC-AL request queues; first and second FC-AL reply queues; first and second FC-AL control registers; first and second FC-AL data direct memory access registers; a PCI to PCI bridge; a PCI to PCI bus switch said first and second AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic adapted for connection to a computer system random access memory; said first and second AGP data and control logic connected to said first and second AGP request and reply queues, respectively; said first and second AGP data and control logic adapted for connection to first and second AGP interfaces; said first and second arbiters adapted for connection to the first and second AGP interfaces; said first and second AGP request and reply queues connected to a host bus interface, said host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto; a host to PCI bus bridge connected to said host bus interface and adapted for connection to a computer system primary PCI bus; said PCI to PCI bus switch is connected between said PCI to PCI bridge and said first and second AGP interfaces, wherein said PCI to PCI bridge transfers PCI information transactions between said host to primary PCI bus bridge and said first and second AGP data and control logic; said first and second FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said first and second FC-AL control register connected to said first and second FC-AL request and reply queues, respectively; first and second FC-AL data direct memory access registers connected to said first and second FC-AL control registers, respectively; and said first and second arbiters, said first and second FC-AL data direct memory access registers and said first and second FC-AL control registers adapted for connection to first and second FC-AL logic circuits.

Claim 26

A core logic chipset configurable for two accelerated graphics port (AGP) interfaces, an AGP interface and a Fibre Channel Arbitrated Loop (FC-AL) interface, or two FC-AL interfaces, comprising: first and second accelerated graphics port (AGP) request queues; first and second AGP reply queues; first and second AGP data and control logic; first and second arbiters; first and second FC-AL request queues; first and second FC-AL reply queues; first and second FC-AL control registers; first and second FC-AL data direct memory access registers; a PCI to PCI bridge; a PCI to PCI bus switch said first and second AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic adapted for connection to a computer system random access memory; said first and second AGP data and control logic connected to said first and second AGP request and reply queues, respectively; said first and second AGP data and control logic adapted for connection to first and second AGP interfaces; said first and second arbiters adapted for connection to the first and second AGP interfaces; said first and second AGP request and reply queues connected to a host bus interface, said host bus interface adapted for connection to a computer system host bus having at least one central processing united connected thereto; a host to PCI bus bridge connected to said host bus interface and adapted for connection to a computer system primary PCI bus; said PCI to PCI bus switch is connected between said PCI to PCI bridge and said first and second AGP interfaces, wherein said PCI to PCI bridge transfers PCI information transactions between said host to primary PCI bus bridge and said first and second AGP data and control logic; said first and second FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said first and second FC-AL control register connected to said first and second FC-AL request and reply queues, respectively; first and second FC-AL data direct memory access registers connected to said first and second FC-AL control registers, respectively; and said first and second arbiters, said first and second FC-AL data direct memory access registers and said first and second FC-AL control registers adapted for connection to first and second FC-AL logic circuits.

Claim 27

A computer system having a core logic chipset configurable for two accelerated graphics port (AGP) interfaces, an AGP interface and a Fibre Channel Arbitrated Loop (FC-AL) interface, or two FC-AL interfaces, and connects a computer processor and memory thereto, said system comprising: at least one central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chipset connected to the host bus and the random access memory bus; said core logic chipset comprising; first and second accelerated graphics port (AGP) request queues; first and second AGP reply queues; first and second AGP data and control logic; first and second arbiters; first and second FC-AL request queues; first and second FC-AL reply queues; first and second FC-AL control registers; first and second FC-AL data direct memory access registers; a PCI to PCI bridge; a PCI to PCI bus switch said first and second AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic connected to said random access memory; said first and second AGP data and control logic connected to said first and second AGP request and reply queues, respectively; said first and second AGP data and control logic connected to first and second AGP interfaces, respectively; said first and second arbiters connected to said first and second AGP interfaces, respectively; said first and second AGP request and reply queues connected to a host bus interface, said host bus interface connected to said host bus; a host to PCI bus bridge connected to said host bus interface and connected to a primary PCI bus; said PCI to PCI bus switch is connected between said PCI to PCI bridge and said first and second AGP interfaces, wherein said PCI to PCI bridge transfers PCI information transactions between said host to primary PCI bus bridge and said first and second AGP data and control logic; said first and second FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said first and second FC-AL control register connected to said first and second FC-AL request and reply queues, respectively; first and second FC-AL data direct memory access registers connected to said first and second FC-AL control registers, respectively; and said first and second arbiters, said first and second FC-AL data direct memory access registers and said first and second FC-AL control registers connected to first and second FC-AL interfaces, respectively; wherein, said core logic chipset configured as an interface bridge between the host bus and said first AGP interface if a first configuration signal is present, or as an interface bridge between the host bus and said first FC-AL interface if a second configuration signal is present; said core logic chipset configured as an interface bridge between the host bus and said second AGP interface if a third configuration signal is present, or as an interface bridge between the host bus and said second FC-AL interface if a fourth configuration signal is present; said core logic chipset configured as an interface bridge between the random access memory bus and said first AGP interface if the first configuration signal is present, or as an interface bridge between the random access memory bus and said first FC-AL interface if the second configuration signal is present; and said core logic chipset configured as an interface bridge between the random access memory bus and said second AGP interface if the third configuration signal is present, or as an interface bridge between the random access memory bus and said second FC-AL interface if the fourth configuration signal is present.

Claim 28

A computer system having a core logic chipset configurable for two accelerated graphics port (AGP) interfaces, an AGP interface and a Fibre Channel Arbitrated Loop (FC-AL) interface, or two FC-AL interfaces, and connects a computer processor and memory thereto, said system comprising: at least one central processing unit connected to a host bus; a random access memory connected to a random access memory bus; a core logic chipset connected to the host bus and the random access memory bus; said core logic chipset comprising; first and second accelerated graphics port (AGP) request queues; first and second AGP reply queues; first and second AGP data and control logic; first and second arbiters; first and second FC-AL request queues; first and second FC-AL reply queues; first and second FC-AL control registers; first and second FC-AL data direct memory access registers; a PCI to PCI bridge; a PCI to PCI bus switch said first and second AGP request and reply queues connected to a memory interface and control logic, said memory and interface control logic connected to said random access memory; said first and second AGP data and control logic connected to said first and second AGP request and reply queues, respectively; said first and second AGP data and control logic connected to first and second AGP interfaces, respectively; said first and second arbiters connected to said first and second AGP interfaces, respectively; said first and second AGP request and reply queues connected to a host bus interface, said host bus interface connected to said host bus; a host to PCI bus bridge connected to said host bus interface and connected to a primary PCI bus; said PCI to PCI bus switch is connected between said PCI to PCI bridge and said first and second AGP interfaces, wherein said PCI to PCI bridge transfers PCI information transactions between said host to primary PCI bus bridge and said first and second AGP data and control logic; said first and second FC-AL request and reply queues connected to said memory interface and control logic and to said host bus interface; said first and second FC-AL control register connected to said first and second FC-AL request and reply queues, respectively; first and second FC-AL data direct memory access registers connected to said first and second FC-AL control registers, respectively; and said first and second arbiters, said first and second FC-AL data direct memory access registers and said first and second FC-AL control registers connected to first and second FC-AL interfaces, respectively; wherein, said core logic chipset configured as an interface bridge between the host bus and said first AGP interface if a first configuration signal is present, or as an interface bridge between the host bus and said first FC-AL interface if a second configuration signal is present; said core logic chipset configured as an interface bridge between the host bus and said second AGP interface if a third configuration signal is present, or as an interface bridge between the host bus and said second FC-AL interface if a fourth configuration signal is present; said core logic chipset configured as an interface bridge between the random access memory bus and said first AGP interface if the first configuration signal is present, or as an interface bridge between the random access memory bus and said first FC-AL interface if the second configuration signal is present; and said core logic chipset configured as an interface bridge between the random access memory bus and said second AGP interface if the third configuration signal is present, or as an interface bridge between the random access memory bus and said second FC-AL interface if the fourth configuration signal is present.

Claim 29

The computer system of claim 24, wherein the core logic chipset is at least one integrated circuit.

Claim 30

The computer system of claim 25, further comprising a first signal switch which connects said first AGP interface, if the first configuration signal is present, or connects said first FC-AL interface, if the second configuration signal is present, to external connections on the at least one integrated circuit.

Claim 31

The computer system of claim 25, further comprising a second signal switch which connects said second AGP interface, if the third configuration signal is present, or connects said second FC-AL interface, if the fourth configuration signal is present, to external connections on the at least one integrated circuit.