Add-in board with programmable configuration registers for use in PCI bus computers

Claim 2

An add-in board for using in a PCI computer system comprising: a first bus; a sub-assembly means coupled to the first bus; said sub-assembly means performing predetermined functions to accomplish a desired task; a microprocessor coupled to the first bus; a non-volatile storage means coupled to the first bus, said non-volatile storage means storing configuration information; a Peripheral Component Interconnect (PCI) bus interface chip interconnected to the first bus and a second bus, said PCI bus interface chip including programmable configuration registers accessible by a PCI microprocessor, over the second bus, and the microprocessor; and a PCI bus interface chip controller responsive to a first signal to inhibit the PCI microprocessor from accessing said configuration registers until the microprocessor pre-loads the configuration information into the said configuration registers.

Claim 3

The add-in board of claim 1 wherein the first signal includes a power-on signal.

Claim 4

The add-in board of claim 1 or 2 wherein the sub-assembly means performs predetermined functions to accomplish the desired task of a communication controller which attaches said PCI system to a Local Area Network; (LAN).

Claim 5

The add-in board of claim 3 wherein the LAN includes ethernet, token ring, Fiber Data Distribution Interface (FDDI) or Asynchronous Transfer Mode (ATM).

Claim 6

The add-in board of claim 1 or 2 wherein the sub-assembly means performs the predetermined functions to accomplish the desired task of a device controller.

Claim 7

The add-in board of claim 5 wherein the device controller controls display, multimedia, disk subassembly including recording medium, recording head and controller or co-processor subsystems including Central Processor Unit, ROM, RAM and stored programs.

Claim 8

The add-in board of claims 1 or 2 wherein the PCI bus interface chip controller further includes PCI slave combinatorial logic means being responsive to a set of enabling signals to activate selected control lines in the PCI bus of the PCI system; and a PCI slave state machine being responsive to a final access grant control signal to generate the set of enabling signals.

Claim 9

The add-in board of claim 7 wherein the final access grant signal is being generated from the output of an "OR" logic circuit means and a single bit register, with an output from the single bit register connected to a first input of the "OR" logic circuit means and a second input of the OR logic circuit means being connected to an input pin of said PCI bus interface chip.

Claim 10

In a PCI computer system having a PCI bus to which a PCI processor executing a PCI configuration software is connected and a PCI add-in board is connected to said PCI bus, a method for configuring the PCI add-in board comprising the steps of: providing a set of configuration registers and a control register on the PCI add-in board, with the set of configuration registers being accessible by the PCI processor and a local processor located on the add-in board; on receiving a predetermined signal, a controller on the add-in board activates a predetermined set of control signals on the PCI bus which causes the PCI processor to delay accessing the set of configuration registers; using the local processor to download configuration data stored in said processor into the set of configuration registers; upon completing loading of the set of configuration registers, notifying the controller which deactivates the set of control signals which was previously activated, thereby allowing the PCI processor to access the set of configuration registers and configuring said PCI add-in board.

Claim 11

In a PCI computer system having a PCI bus to which a PCI processor executing a PCI configuration software is connected and a PCI add-in board is connected to said PCI bus, a method for configuring the PCI add-in board comprising the steps of: providing a set of configuration registers and a control register on the PCI add-in board, with the set of configuration registers being accessible by the PCI processor and a local processor located on the add-in board; on receiving a predetermined signal, a controller on the add-in board activates a predetermined set of control signals on the PCI bus which causes the PCI processor to delay accessing the set of configuration registers; using the local processor to download configuration data stored in said processor into the set of configuration registers; upon completing loading of the set of configuration registers, notifying the controller which deactivates the set of control signals which was previously activated, thereby allowing the PCI processor to access the set of configuration registers and configuring said PCI add-in board.

Claim 12

An interface subsystem for coupling add-in boards to the PCI bus of a PCI computer system comprising: at least one configuration register for storing configuration data; a control register for storing control information; a PCI bus interface controller being responsive to a first signal to activate selected signals, on the PCI bus, into a first state which inhibits a PCI processor from accessing said at least one configuration register; and a circuit arrangement for monitoring the control register and depending on the state of one or more selected bits in said register outputs a second signal which causes the PCI bus interface controller to deactivate the selected signals, on the PCI bus, into a second state to enable the PCI processor to access the at least one configuration register.

Claim 13

An interface subsystem for coupling add-in boards to the PCI bus of a PCI computer system comprising: at least one configuration register for storing configuration data; a control register for storing control information; a PCI bus interface controller being responsive to a first signal to activate selected signals, on the PCI bus, into a first state which inhibits a PCI processor from accessing said at least one configuration register; and a circuit arrangement for monitoring the control register and depending on the state of one or more selected bits in said register outputs a second signal which causes the PCI bus interface controller to deactivate the selected signals, on the PCI bus, into a second state to enable the PCI processor to access the at least one configuration register.

Claim 14

The interface subsystem of claim 10 further including functional registers which can be written and read by the PCI processor over the PCI bus.

Claim 15

The interface subsystem of claim 10 wherein the first signal is a power-on signal.

Claim 16

The interface subsystem of claim 10 wherein the PCI bus interface means includes a combinatorial logic circuit arrangement with outputs coupled to the PCI bus and a controller coupled to inputs of said combinatorial logic circuit arrangement.

Claim 17

The interface subsystem of claim 13 wherein the controller includes a state machine.

Claim 18

The interface subsystem of claim 10 wherein the circuit means includes a logic "OR" circuit having an output coupled to the PCI bus interface means and two inputs one of which is coupled to the register means; and a conductor for providing a control signal from an external source connected to another one of the two inputs.

Claim 19

The interface subsystem of claim 10 wherein the external source includes a pin mounted on said interface subsystem.

Claim 20

An add-in board for use in a computer system comprising: a bus; a task generator coupled to the bus, said task generator including circuitry which performs required functions to accomplish a desired task; a storage including configuration information coupled to the bus; a Peripheral Component Interconnect (PCI) bus interface chip including programmable Configuration Registers; a controller including logic circuit and a register for controlling access to the Configuration Registers; and a microprocessor coupled to the bus, said microprocessor responsive to a signal to load configuration information into the Configuration Registers and activate the controller wherein a processor associated with said computer system is given access to said Configuration Registers to configure the Add-in Board.

Claim 21

An add-in board for use in a computer system comprising: a bus; a task generator coupled to the bus, said task generator including circuitry which performs required functions to accomplish a desired task; a storage including configuration information coupled to the bus; a Peripheral Component Interconnect (PCI) bus interface chip including programmable Configuration Registers; a controller including logic circuit and a register for controlling access to the Configuration Registers; and a microprocessor coupled to the bus, said microprocessor responsive to a signal to load configuration information into the Configuration Registers and activate the controller wherein a processor associated with said computer system is given access to said Configuration Registers to configure the Add-in Board.

Claim 22

The Add-in Board of claim 17 wherein the task generator includes an adapter for attaching to a LAN.

Claim 23

The Add-in Board of claim 17 wherein the task generator includes a device controller.

Claim 24

In a computer system comprising a processor and an adapter card coupled to the bus of the processor, a method for configuring the adapter card comprising the steps of: (a) providing programmable configuration registers, on the adapter card; (b) providing circuitry, on the adapter card, which outputs electrical signals that cause the processor to access or not access the configuration registers; (c) activating the circuitry to generate the electrical signals denying the processor access to said configuration registers; (d) using a processor on the adapter card to load configuration information into said configuration registers; and (e) activating the circuitry to generate electrical signals allowing said processor to access said configuration registers to configure said adapter card.

Claim 25

In a computer system comprising a processor and an adapter card coupled to the bus of the processor, a method for configuring the adapter card comprising the steps of: (a) providing programmable configuration registers, on the adapter card; (b) providing circuitry, on the adapter card, which outputs electrical signals that cause the processor to access or not access the configuration registers; (c) activating the circuitry to generate the electrical signals denying the processor access to said configuration registers; (d) using a processor on the adapter card to load configuration information into said configuration registers; and (e) activating the circuitry to generate electrical signals allowing said processor to access said configuration registers to configure said adapter card.

Claim 26

The interface subsystem of claim 10 wherein the at least one configuration register is programmable.