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US6054886A
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Reference buffer technique for high speed switched capacitor circuits
Assignee: National Semiconductor Corp
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Filing: 1997-09-18
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Granted: 2000-04-25
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Expires: 2017-09-18
Abstract
Abstract A low power reference buffer includes a new amplifier design with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.
Inventors
- 👤 Ion E. Opris
- 👤 Laurence Douglas Lewicki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:47
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
117 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a common node; a capacitance coupled between said common node and a reference terminal; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node.
Claim 2
Independent Claim
117 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a common node; a capacitance coupled between said common node and a reference terminal; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node.
Claim 3
Dependent Claim
24 words
The apparatus of claim 1 wherein said first amplifier first input terminal is non-inverting and wherein said first amplifier second input terminal is inverting.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1 further including a resistance coupled between said third inductance and a reference node.
Claim 5
Independent Claim
184 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input and said common node; and a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier out put terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 6
Independent Claim
184 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input and said common node; and a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier out put terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 7
Dependent Claim
14 words
The apparatus of claim 4 wherein said first and second reference signals are equal.
Claim 8
Dependent Claim
24 words
The apparatus of claim 4 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 9
Dependent Claim
133 words
The apparatus of claim 4 so wherein said first amplifier includes a voltage gain amplifier coupled to an adaptive biasing transconductance stage in series thereto, said voltage gain amplifier comprising: a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 10
Dependent Claim
24 words
The apparatus of claim 5 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 11
Dependent Claim
132 words
The apparatus of claim 8 wherein said first amplifier includes a voltage gain amplifier coupled to an adaptive biasing transconductance stage in series thereto, said voltage gain amplifier comprising: a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 12
Dependent Claim
132 words
The apparatus of claim 6 wherein said first amplifier includes a voltage gain amplifier coupled to an adaptive biasing transconductance stage in series thereto, said voltage gain amplifier comprising: a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 13
Independent Claim
183 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 14
Independent Claim
183 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 15
Dependent Claim
14 words
The apparatus of claim 11 wherein said first and second reference signals are equal.
Claim 16
Dependent Claim
24 words
The apparatus of claim 12 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 17
Dependent Claim
24 words
The apparatus of claim 11 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 18
Independent Claim
137 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said first amplifier including a voltage gain amplifier coupled in series to an adaptive biasing transconductance stage in series thereto; a common node; a capacitance coupled between said common node and a reference terminal; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node.
Claim 19
Independent Claim
137 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said first amplifier including a voltage gain amplifier coupled in series to an adaptive biasing transconductance stage in series thereto; a common node; a capacitance coupled between said common node and a reference terminal; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node.
Claim 20
Independent Claim
238 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said first amplifier including a voltage gain amplifier coupled in series to an adaptive biasing transconductance stage in series thereto; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; and further wherein said voltage gain amplifier comprises: a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said first reference signal and said first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 21
Independent Claim
238 words
An apparatus including a reference buffer, comprising: a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said first amplifier including a voltage gain amplifier coupled in series to an adaptive biasing transconductance stage in series thereto; a common node; an output terminal; a first inductance coupled between said first amplifier output terminal and said common node; a second inductance coupled between said first amplifier second input terminal and said common node; a third inductance coupled to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; and further wherein said voltage gain amplifier comprises: a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said first reference signal and said first input transistor second terminal configured to receive a first bias signal; a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and a plurality of diodes coupled to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 22
Dependent Claim
15 words
The apparatus of claim 16 wherein said first and second input transistors are pMOS transistors.
Claim 23
Dependent Claim
14 words
The apparatus of claim 16 wherein said first and second input transistors are matched.
Claim 24
Independent Claim
191 words
A method of providing a reference buffer, comprising the steps of: providing a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; providing a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; providing a common node; providing an output terminal; coupling a first inductance between said first amplifier output terminal and said common node; coupling a second inductance between said first amplifier second input and said common node; and coupling a third inductance to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 25
Independent Claim
191 words
A method of providing a reference buffer, comprising the steps of: providing a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal; providing a second amplifier having a second amplifier first input terminal, a second amplifier second input terminal and a second amplifier output terminal; providing a common node; providing an output terminal; coupling a first inductance between said first amplifier output terminal and said common node; coupling a second inductance between said first amplifier second input and said common node; and coupling a third inductance to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; wherein said second amplifier output terminal and said second amplifier second input terminal are coupled to said third inductance such that said second amplifier output terminal and second amplifier second input terminal are separated from said common node; and further wherein said second amplifier first input terminal is configured to receive a second reference signal.
Claim 26
Dependent Claim
14 words
The method of claim 19 wherein said first and second reference signals are equal.
Claim 27
Dependent Claim
24 words
The method of claim 20 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 28
Dependent Claim
148 words
The method of claim 21 wherein said step of providing said first amplifier includes the step of coupling a voltage gain amplifier to an adaptive biasing transconductance stage in series thereto, said step of coupling said voltage gain amplifier comprising the steps of: providing a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; providing a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and coupling a plurality of diodes to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 29
Dependent Claim
24 words
The method of claim 19 wherein said second amplifier first input terminal is non-inverting and wherein said second amplifier second input terminal is inverting.
Claim 30
Dependent Claim
148 words
The method of claim 23 wherein said step of providing said first amplifier includes the step of coupling a voltage gain amplifier to an adaptive biasing transconductance stage in series thereto, said step of coupling said voltage gain amplifier comprising the steps of: providing a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; providing a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and coupling a plurality of diodes to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 31
Dependent Claim
148 words
The method of claim 19 wherein said step of providing said first amplifier includes the step of coupling a voltage gain amplifier to an adaptive biasing transconductance stage in series thereto, said step of coupling said voltage gain amplifier comprising the steps of: providing a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said reference signal and said first input transistor second terminal configured to receive a first bias signal; providing a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and coupling a plurality of diodes to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 32
Independent Claim
261 words
A method of providing a reference buffer, comprising the steps of: providing a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said step of providing said first amplifier including the step of coupling a voltage gain amplifier in series to an adaptive biasing transconductance stage in series thereto; providing a common node; providing an output terminal; coupling a first inductance between said first amplifier output terminal and said common node; coupling a second inductance between said first amplifier second input terminal and said common node; coupling a third inductance to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; and further wherein said step of coupling said voltage gain amplifier comprises the steps of: providing a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said first reference signal and said first input transistor second terminal configured to receive a first bias signal; providing a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and coupling a plurality of diodes to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 33
Independent Claim
261 words
A method of providing a reference buffer, comprising the steps of: providing a first amplifier having first and second input terminals and an output terminal, said first amplifier first input terminal configured to receive a first reference signal, said step of providing said first amplifier including the step of coupling a voltage gain amplifier in series to an adaptive biasing transconductance stage in series thereto; providing a common node; providing an output terminal; coupling a first inductance between said first amplifier output terminal and said common node; coupling a second inductance between said first amplifier second input terminal and said common node; coupling a third inductance to said common node and said output terminal; wherein said first inductance and said second inductance separate said first amplifier output terminal, and said first amplifier second input terminal, respectively, from said common node; and further wherein said step of coupling said voltage gain amplifier comprises the steps of: providing a first input transistor having first, second and third terminals, said first input transistor first terminal configured to receive said first reference signal and said first input transistor second terminal configured to receive a first bias signal; providing a second input transistor having first, second and third terminals, said second input transistor second terminal configured to receive a second bias signal; and coupling a plurality of diodes to said second terminals of said first and second input transistors; wherein said second input transistor third terminal is coupled to said first input transistor third terminal, said third terminals further configured to receive a third bias signal.
Claim 34
Dependent Claim
15 words
The method of claim 26 wherein said first and second input transistors are pMOS transistors.
Claim 35
Dependent Claim
14 words
The method of claim 26 wherein said first and second input transistors are matched.
References Cited (Backward Citations)
US5517130A
Cited
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