Stabilizing circuit and amplifier

Claim 2

A stabilizing circuit for stabilizing a transistor, comprising: a first capacitor being directly connected between an input node receiving an input signal and an input-side electrode of said transistor; and a first resistor being directly connected between said input node and a prescribed reference potential, wherein the values of said first capacitor and said first resistor are set so that said first resistor consumes power in a predetermined low-frequency domain thereby preventing said transistor from oscillation in the low-frequency domain.

Claim 3

The stabilizing circuit in accordance with claim 1, further comprising a second resistor being connected between said input-side electrode of said transistor and said reference potential, wherein the values of said first capacitor, said first resistor and said second resistor are set so that said second resistor consumes power in a predetermined high-frequency domain thereby preventing said transistor from oscillation in high-frequency domain. further comprising a second

Claim 4

The stabilizing circuit in accordance with claim 1, further comprising a second capacitor being connected between an output-side electrode of said transistor and said reference potential.

Claim 5

The stabilizing circuit in accordance with claim 1, further comprising an inductance and a second capacitor being connected in series between an output-side electrode of said transistor and said reference potential.

Claim 6

The stabilizing circuit in accordance with claim 4, wherein said inductance includes a transmission line.

Claim 7

The stabilizing circuit in accordance with claim 2, further comprising an inductance and a second capacitor being connected in series between an output-side electrode of said transistor and said reference potential.

Claim 8

The stabilizing circuit in accordance with claim 6, wherein said inductance includes a transmission line.

Claim 9

The stabilizing circuit in accordance with claim 1, wherein the capacitance value C 0 of said first capacitor and the resistance value R 0 of said first resistor satisfy the following relation: ##EQU15## in relation to the input capacitance C gs of said transistor, the angular frequency ω 0 of a signal to be transmitted and the angular frequency ω L of a low-frequency component to be suppressed.

Claim 10

The stabilizing circuit in accordance with claim 2, wherein the capacitance value C 0 of said first capacitor, the resistance value R 0 of said first resistor and the resistance value R 1 of said second resistor satisfy the following relations: ##EQU16## in relation to the input capacitance C gs of said transistor, the angular frequency ω 0 of a signal to be transmitted and the angular frequency ω L of a low-frequency component to be suppressed.

Claim 11

The stabilizing circuit in accordance with claim 5, wherein the characteristic impedance Z a and the length L a of said transmission line and the capacitance value C 1 of said second capacitor satisfy the following relation: ##EQU17## in relation to the angular frequency ω H and the wave length λ H of a high-frequency component to be suppressed.

Claim 12

The stabilizing circuit in accordance with claim 7, wherein the characteristic impedance Z a and the length L a of said transmission line and the capacitance value C 1 of said second capacitor satisfy the following relation: ##EQU18## in relation to the angular frequency ω H and the wave length λ H of a high-frequency component to be suppressed.

Claim 13

An amplifier comprising: a transistor; a first capacitor being directly connected between an input node receiving an input signal and an input-side electrode of said transistor; and a first resistor being directly connected between said input node and a prescribed reference potential, wherein the values of said first capacitor and said first resistor are set so that said first resistor consumes power in a predetermined low-frequency domain thereby preventing said transistor from oscillation in the low-frequency domain.

Claim 14

An amplifier comprising: a transistor; a first capacitor being directly connected between an input node receiving an input signal and an input-side electrode of said transistor; and a first resistor being directly connected between said input node and a prescribed reference potential, wherein the values of said first capacitor and said first resistor are set so that said first resistor consumes power in a predetermined low-frequency domain thereby preventing said transistor from oscillation in the low-frequency domain.

Claim 15

The amplifier in accordance with claim 12, further comprising a second capacitor being connected between an output-side electrode of said transistor and said reference potential.

Claim 16

The amplifier in accordance with claim 12, further comprising an inductance and a second capacitor being connected in series between an output-side electrode of said transistor and said reference potential.

Claim 17

The amplifier in accordance with claim 14, wherein said inductance includes a line.

Claim 18

The amplifier in accordance with claim 12, wherein the capacitance value C 0 of said first capacitor and the resistance value R 0 of said first resistor satisfy the following relation: ##EQU19## in relation to the input capacitance C gs of said transistor, the angular frequency ω 0 of a signal to be transmitted and the angular frequency ω L of a low-frequency component to be suppressed.

Claim 19

The amplifier in accordance with claim 13, wherein the capacitance value C 0 of said first capacitor, the resistance value R 0 of said first resistor and the resistance value R 1 of a second resistor satisfy the following relations: ##EQU20## in relation to the input capacitance C gs of said transistor, the angular frequency ω 0 of a signal to be transmitted and the angular frequency ω L of a low-frequency component to be suppressed.

Claim 20

The amplifier in accordance with claim 12, further comprising a second resistor being connected between said input-side electrode of said transistor and said reference potential, wherein the values of said first capacitor, said first resistor and said second resistor are set so that said second resistor consumes power in a predetermined high-frequency domain thereby preventing said transistor from oscillation in the high-frequency domain.

Claim 21

The amplifier in accordance with claim 15, wherein the characteristic impedance Z a and the length L a of said transmission line and the capacitance value C 1 of said second capacitor satisfy the following relation: ##EQU21## in relation to the angular frequency ω H and the wave length λ H of a high-frequency component to be suppressed.

Claim 22

The amplifier in accordance with claim 12, wherein said transistor is a field-effect transistor.

Claim 23

An amplifier comprising: first and second transistors; a first capacitor being connected between a first input node receiving an input signal and an input-side electrode of said first transistor; a first resistor being connected between said first input node and a prescribed reference potential; a second capacitor being connected between a second input node receiving an input signal and an input-side electrode of said second transistor; a second resistor being connected between said second input node and said reference potential; a third capacitor being connected between an output-side electrode of said first transistor and said reference potential; and a transmission line and a fourth capacitor being connected in series between an output-side electrode of said second transistor and said reference potential, one of said first and second transistors being provided on a front stage, the other one of said first and second transistors being provided on a rear stage.

Claim 24

An amplifier comprising: first and second transistors; a first capacitor being connected between a first input node receiving an input signal and an input-side electrode of said first transistor; a first resistor being connected between said first input node and a prescribed reference potential; a second capacitor being connected between a second input node receiving an input signal and an input-side electrode of said second transistor; a second resistor being connected between said second input node and said reference potential; a third capacitor being connected between an output-side electrode of said first transistor and said reference potential; and a transmission line and a fourth capacitor being connected in series between an output-side electrode of said second transistor and said reference potential, one of said first and second transistors being provided on a front stage, the other one of said first and second transistors being provided on a rear stage.

Claim 25

The stabilizing circuit in accordance with claim 1, further comprising a second capacitor being directly connected between an output-side electrode of said transistor and said reference potential.

Claim 26

The stabilizing circuit in accordance with claim 1, further comprising an inductance and a second capacitor being directly connected in series between an output-side electrode of said transistor and said reference potential.

Claim 27

The stabilizing circuit in accordance with claim 2, further comprising an inductance and a second capacitor being directly connected in series between an output-side electrode of said transistor and said reference potential.

Claim 28

The amplifier in accordance with claim 12, further comprising a second capacitor being directly connected between an output-side electrode of said transistor and said reference potential.

Claim 29

The amplifier in accordance with claim 12, further comprising an inductance and a second capacitor being directly connected in series between an output-side electrode of said transistor and said reference potential.