US6052008A
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Generation of true and complement signals in dynamic circuits
Assignee: International Business Machines Corp
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Filing: 1997-07-14
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Granted: 2000-04-18
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Expires: 2017-07-14
Abstract
Abstract A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
Inventors
- 👤 Sam Gat-Shang Chu
- 👤 Visweswaya Rao Kodali
- 👤 Michael Ju Hyeok Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
A circuit, comprising: an inverting circuit coupled to a first input signal for generating and outputting a second signal, the second signal is a complement of the first input signal; a logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output; a second n-channel FET having a gate electrode, the second n-channel FET operable for receiving said first signal at the gate electrode, and wherein the second n-channel FET is coupled to the output, and wherein the first signal is a dynamic input signal; and a second p-channel FET having a gate electrode, the second p-channel FET operable for receiving a clock signal at the gate electrode and coupled to the output of the first logic circuit.
Claim 2
Dependent Claim
173 words
A circuit, comprising: an inverting circuit coupled to a first input signal for generating and outputting a second signal, the second signal is a complement of the first input signal; a logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output; a second n-channel FET having a gate electrode, the second n-channel FET operable for receiving said first signal at the gate electrode, and wherein the second n-channel FET is coupled to the output, and wherein the first signal is a dynamic input signal; and a second p-channel FET having a gate electrode, the second p-channel FET operable for receiving a clock signal at the gate electrode and coupled to the output of the first logic circuit.
Claim 3
Dependent Claim
24 words
A circuit in accordance with claim 1 wherein the logic circuit is operable for outputting to the output an evaluation of the second signal.
Claim 4
Dependent Claim
15 words
A circuit in accordance with claim 1 wherein the second signal is a static signal.
Claim 5
Dependent Claim
18 words
A circuit in accordance with claim 1 wherein the first p-channel FET is coupled to a voltage reference.
Claim 6
Dependent Claim
197 words
A logic circuit, comprising: a first logic circuit outputting a first output signal; an inverting circuit coupled to the first output signal for generating and outputting a second signal, the second signal is a complement of the first output signal; a second logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output; a second n-channel FET having a gate electrode, the second n-channel FET operable for receiving said first output signal at the gate electrode, and wherein the second n-channel FET is coupled to the output, and wherein the first output signal is a dynamic input signal, wherein the first p-channel FET is coupled to a voltage reference; and a second p-channel FET having a gate electrode, the second p-channel FET operable for receiving a clock signal at the gate electrode and coupled to the output of the second logic circuit.
Claim 7
Dependent Claim
197 words
A logic circuit, comprising: a first logic circuit outputting a first output signal; an inverting circuit coupled to the first output signal for generating and outputting a second signal, the second signal is a complement of the first output signal; a second logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output; a second n-channel FET having a gate electrode, the second n-channel FET operable for receiving said first output signal at the gate electrode, and wherein the second n-channel FET is coupled to the output, and wherein the first output signal is a dynamic input signal, wherein the first p-channel FET is coupled to a voltage reference; and a second p-channel FET having a gate electrode, the second p-channel FET operable for receiving a clock signal at the gate electrode and coupled to the output of the second logic circuit.
Claim 8
Dependent Claim
25 words
A circuit in accordance with claim 5 wherein the second logic circuit is operable for outputting to the output an evaluation of the second signal.
Claim 9
Dependent Claim
105 words
A logic circuit comprising: first circuitry operable for inverting an output signal from a dynamic logic circuit to generate a first input signal; second circuitry operable for receiving a clock signal that causes the logic circuit to operate in alternating precharge and evaluate phases; third circuitry operable for receiving the first input signal and operable for evaluating the first input signal during the evaluate phase; and fourth circuitry receiving the first input signal and operable for causing the logic circuit to correctly evaluate the first input signal when the first input signal switches from a high level to a low level during the evaluate phase.
Claim 10
Dependent Claim
105 words
A logic circuit comprising: first circuitry operable for inverting an output signal from a dynamic logic circuit to generate a first input signal; second circuitry operable for receiving a clock signal that causes the logic circuit to operate in alternating precharge and evaluate phases; third circuitry operable for receiving the first input signal and operable for evaluating the first input signal during the evaluate phase; and fourth circuitry receiving the first input signal and operable for causing the logic circuit to correctly evaluate the first input signal when the first input signal switches from a high level to a low level during the evaluate phase.
Claim 11
Dependent Claim
40 words
A logic circuit in accordance with claim 7 wherein the third circuitry operable for receiving the first input signal further receiving said output signal and operable for evaluating the first input signal and the output signal during the evaluate phase.
Claim 12
Dependent Claim
37 words
A logic circuit in accordance with claim 7 further comprising circuitry operable for outputting an evaluation of the first input signal, and wherein the fourth circuitry for causing the logic circuit to correctly evaluate comprises a FET.
Claim 13
Dependent Claim
121 words
A logic circuit in accordance with claim 7 wherein the second circuitry operable for receiving the clock signal comprises a first p-channel FET having a gate electrode operable for receiving the clock signal, the first p-channel FET coupled between a first voltage reference and a node, and wherein the third circuitry operable for evaluating is coupled to the node and comprises a first n-channel FET operable for receiving said, first input signal and a second n-channel FET operable for receiving a said output signal, and wherein the fourth circuitry operable for causing comprises a second p-channel FET having a gate electrode operable for receiving the first input signal, the second p-channel FET coupled between the node and the first voltage reference.
Claim 14
Dependent Claim
194 words
A data processing system comprising a plurality of devices including a processor, a storage device, a random access memory, a display device, and an input device coupled together by a bus and wherein one of the plurality of devices comprises logic circuitry comprising: a first logic circuit outputting a first output signal wherein said first output signal is a dynamic input signal; an inverting circuit coupled to the first output signal for generating and outputting a second signal, the second signal is a complement of the first output signal; and a second logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output and wherein the second signal is a static signal; a second p-channel FET operable for receiving a clock signal at its gate electrode, the first p-channel FET coupled between a voltage reference and the output node.
Claim 15
Dependent Claim
194 words
A data processing system comprising a plurality of devices including a processor, a storage device, a random access memory, a display device, and an input device coupled together by a bus and wherein one of the plurality of devices comprises logic circuitry comprising: a first logic circuit outputting a first output signal wherein said first output signal is a dynamic input signal; an inverting circuit coupled to the first output signal for generating and outputting a second signal, the second signal is a complement of the first output signal; and a second logic circuit comprising, an output, and a first n-channel FET having a gate electrode, the first n-channel FET receiving the second signal at the gate electrode and operably coupling to the output, a first p-channel FET having a gate electrode, the gate electrode of the first p-channel FET coupled to the gate electrode of the first n-channel FET, the first p-channel FET coupled to the output and wherein the second signal is a static signal; a second p-channel FET operable for receiving a clock signal at its gate electrode, the first p-channel FET coupled between a voltage reference and the output node.
Claim 16
Dependent Claim
34 words
A data processing system in accordance with claim 11 further comprising a second n-channel FET having a gate electrode operable for receiving said dynamic input signal, the second n-channel FET coupled to the output.
Claim 17
Dependent Claim
19 words
The data processing system in accordance with claim 12 further comprising an output latch circuit coupled to the output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-18 | 2003-10-18 | 2004-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-18 | 2007-10-18 | 2008-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-18 | 2011-10-18 | 2012-04-18 | $7700.00 | Window Closed / Lapsed |