US6049895A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Failure analyzer with distributed data processing network and method used therein
Assignee: NEC Corp
•
Filing: 1997-12-08
•
Granted: 2000-04-11
•
Expires: 2017-12-08
Abstract
Abstract A failure analyzer has an electric characteristic inspection system for producing pieces of electric test data information for integrated circuit devices fabricated on a semiconductor wafer, a visual inspection system for producing pieces of appearance test data information for the semiconductor wafer and a data analyzing system for producing a failure analysis report from the pieces of electric test data information and the pieces of appearance test data information, and the data analyzing system is implemented by using a client-server network technology so as to increase a data processing capability depending upon the amount of data to be analyzed.
Inventors
- 👤 Masaaki Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193; G01R31/31935; G01R31/3185; G01R31/318505; G01R31/318511
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
107 words
A failure analyzer for analyzing pieces of test data information having pieces of appearance test data information and pieces of electric test data information, comprising: a test system including a visual inspection sub-system carrying out an appearance test for a semiconductor wafer so as to produce said pieces of appearance test data information, and an electric characteristic inspection sub-system carrying out electric tests for integrated circuit devices fabricated on said semiconductor wafer for producing said pieces of electric test data information; and a data analyzing system connected to said test system for analyzing said pieces of test data information, and implemented by using a client-server network technology.
Claim 2
Dependent Claim
107 words
A failure analyzer for analyzing pieces of test data information having pieces of appearance test data information and pieces of electric test data information, comprising: a test system including a visual inspection sub-system carrying out an appearance test for a semiconductor wafer so as to produce said pieces of appearance test data information, and an electric characteristic inspection sub-system carrying out electric tests for integrated circuit devices fabricated on said semiconductor wafer for producing said pieces of electric test data information; and a data analyzing system connected to said test system for analyzing said pieces of test data information, and implemented by using a client-server network technology.
Claim 3
Dependent Claim
84 words
The failure analyzer as set forth in claim 1, in which said data analyzing system includes a general analyzer producing a piece of failure analysis report information from pieces of local analysis data information, a plurality of local analyzers for producing said pieces of local analysis data information, a data distributor distributing said pieces of test data information to said plurality of local analysis data information, and a communicating network connected between said general analyzer, said plurality of local analyzers and said data distributor.
Claim 4
Dependent Claim
58 words
The failure analyzer as set forth in claim 2, in which said data distributor produces a small piece of test data information for one of said plurality of local analyzers with a small data processing capability and a large piece of test data information for another of said plurality of local analyzer with a large data processing capability.
Claim 5
Dependent Claim
21 words
The failure analyzer as set forth in claim 2, in which the number of said plurality of local analyzers is changeable.
Claim 6
Independent Claim
127 words
A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of: a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area, and b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis.
Claim 7
Independent Claim
127 words
A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of: a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area, and b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis.
Claim 8
Dependent Claim
28 words
The method as set forth in claim 5, in which said electric components are memory cells, and said first diagnosis and said second diagnosis are defective and non-defective.
Claim 9
Independent Claim
169 words
A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of: a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area; and b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis, wherein a high level-analysis is carried out by assigning coordinates on said semiconductor wafer to each electric defect, as represented in said electric test data information, and results of said high level-analysis are used to determine a pattern of said electric defects.
Claim 10
Independent Claim
169 words
A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of: a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area; and b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis, wherein a high level-analysis is carried out by assigning coordinates on said semiconductor wafer to each electric defect, as represented in said electric test data information, and results of said high level-analysis are used to determine a pattern of said electric defects.
Claim 11
Dependent Claim
27 words
A method as recited in claim 7, wherein said electric components are memory cells, and said first diagnosis and said second diagnosis are defective and non-defective, respectively.
References Cited (Backward Citations)
US3962687A
Cited
US4369511A
Cited
US4460999A
Cited
JPS60134370A
Cited
JPH0230534A
Cited
US5216673A
Cited
US5410687A
Cited
US5219765A
Cited
JPH04299765A
Cited
US5463459A
Cited
JPH0772206A
Cited
JPH07270836A
Cited
JPH084467A
Cited
US5883710A
Cited
US5598341A
Cited
US5610925A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |