US6046104A
Expired / Lapsed
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Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias
Assignee: GlobalFoundries Inc
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Filing: 1998-05-15
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Granted: 2000-04-04
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Expires: 2018-05-15
Abstract
Abstract Via void formation is substantially reduced or eliminated between the steps of depositing a barrier layer on a HSQ gap fill layer, and filling a through-hole with a conductive material deposited on the barrier layer, by performing a low-temperature baking following the deposition of the barrier layer. In particular, a high-temperature, low-pressure degas operation is performed immediately preceding, and in-situ with, the tungsten plug deposition that fills the through-hole to form a via. The low-pressure baking is performed at a high temperature and sufficiently low pressure that is less than the vapor pressure of imparities contained in the HSQ. Hence, any exposed portions of the HSQ gap fill layer that are not covered by the barrier layer (e.g., the titanium nitride (TiN) liner) will be outgassed during the low-pressure baking to minimize the possibility of HSQ outgas during tungsten deposition.
Inventors
- 👤 Nick Kepler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/052; H10W20/0526; H10W20/033; H10W20/034; H10W20/038; H10W20/039; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
169 words
A method of manufacturing a semiconductor device, the method comprising the sequential steps of: forming a first patterned conductive layer, having gaps therein and comprising a first conductive feature, on a first dielectric layer overlying a substrate; depositing a layer of hydrogen silsequioxane (HSQ) filling the gaps; depositing a second dielectric layer on the first patterned conductive layer and on the HSQ gap fill layer; planarizing an upper surface of the second dielectric layer; forming a through-hole in the second dielectric layer exposing a portion of the upper surface and at least a portion of a side surface of the first conductive feature, and penetrating into and exposing at least a portion of the HSQ gap fill layer; depositing a barrier layer on at least a portion of the exposed portions of the HSQ gap fill layer; low pressure baking to drive off impurities contained in the HSQ gap fill layer; and filling the through-hole with a conductive material deposited on the barrier layer to form a borderless via.
Claim 2
Independent Claim
169 words
A method of manufacturing a semiconductor device, the method comprising the sequential steps of: forming a first patterned conductive layer, having gaps therein and comprising a first conductive feature, on a first dielectric layer overlying a substrate; depositing a layer of hydrogen silsequioxane (HSQ) filling the gaps; depositing a second dielectric layer on the first patterned conductive layer and on the HSQ gap fill layer; planarizing an upper surface of the second dielectric layer; forming a through-hole in the second dielectric layer exposing a portion of the upper surface and at least a portion of a side surface of the first conductive feature, and penetrating into and exposing at least a portion of the HSQ gap fill layer; depositing a barrier layer on at least a portion of the exposed portions of the HSQ gap fill layer; low pressure baking to drive off impurities contained in the HSQ gap fill layer; and filling the through-hole with a conductive material deposited on the barrier layer to form a borderless via.
Claim 3
Dependent Claim
26 words
The method according to claim 1, wherein the first patterned conductive layer comprises a metal layer and the first conductive feature comprises a first metal feature.
Claim 4
Dependent Claim
37 words
The method according to claim 2, wherein the metal layer is a composite metal layer comprising: a lower refractory metal layer; an intermediate primary conductive layer comprising aluminum or an aluminum alloy; and an upper anti-reflective coating.
Claim 5
Dependent Claim
31 words
The method according to claim 2, wherein the metal layer comprises a plurality of metal lines having a size no greater than about 0.25 microns, and the gaps comprise interwiring spacings.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein the low pressure baking step comprises baking at a temperature of about 445° C. to 485° C.
Claim 7
Dependent Claim
24 words
The method of claim 5, wherein the low pressure baking step and the conductive material filling step are performed at substantially the same temperatures.
Claim 8
Dependent Claim
29 words
The method of claim 6, wherein the low pressure baking step further comprises baking at a pressure of about 20 Torr for about 10 seconds to about 20 seconds.
Claim 9
Dependent Claim
25 words
The method of claim 5, wherein the low pressure baking step further comprises baking at a pressure of about 20 Torr to about 40 Torr.
Claim 10
Dependent Claim
36 words
The method of claim 8, wherein the low pressure baking step further comprises baking for about 10 seconds to about 20 seconds at a pressure of about 20 Torr and a temperature of about 445° C.
Claim 11
Dependent Claim
49 words
The method of claim 8, wherein the conductive material filling step is performed at a first temperature and first pressure, and the low pressure baking step is performed at a second temperature greater than or equal to the first temperature, and a second pressure less than the first pressure.
Claim 12
Dependent Claim
33 words
The method of claim 1, wherein no intervening wet or thermal processing is performed between the low pressure baking and filling the through-hole with the conductive material stress to form the borderless via.
Claim 13
Dependent Claim
24 words
The method of claim 1, wherein the low pressure baking step and the conductive material filling step are performed in the same reaction chamber.
Claim 14
Dependent Claim
52 words
The method of claim 12, wherein the filling step comprises: concurrently initiating a silane reduction-based tungsten chemical vapor deposition and a hydrogen reduction-based tungsten chemical vapor deposition; and halting the silane reduction-based tungsten chemical vapor deposition a predetermined time after the initiation thereof, while continuing the hydrogen reduction-based tungsten chemical vapor deposition.
Claim 15
Dependent Claim
28 words
The method of claim 1, further comprising a step of vacuum baking following the step of forming the through-hole and before the step of depositing the barrier layer.
Claim 16
Dependent Claim
33 words
The method of claim 14, wherein the vacuum baking step comprises vacuum baking at a first temperature, and the low-pressure baking step comprises baking at a second temperature higher than the first temperature.
Claim 17
Dependent Claim
30 words
The method of claim 15, wherein the step of low pressure baking is performed in the same tool employed for the step of filling the through-hole with the conductive material.
Claim 18
Independent Claim
147 words
A method of manufacturing a semiconductor device, the method comprising the sequential steps of: forming a first patterned conductive layer, having gaps therein and comprising a first conductive feature, on a first dielectric layer overlying a substrate; depositing a layer of hydrogen silsesquioxane (HSQ) filling the gaps; depositing a second dielectric layer on the first patterned conductive layer and on the HSQ gap fill layer; planarizing an upper surface of the second dielectric layer; forming a through-hole in the second dielectric layer exposing at least a portion of the upper surface of the first conductive feature, and exposing at least a portion of the HSQ gap fill layer; vacuum baking to outgas impurities contained in the HSO gap fill layer; low pressure baking to drive off impurities contained in the HSQ gap fill layer; and filling the through-hole with a conductive material deposited on the barrier layer.
Claim 19
Independent Claim
147 words
A method of manufacturing a semiconductor device, the method comprising the sequential steps of: forming a first patterned conductive layer, having gaps therein and comprising a first conductive feature, on a first dielectric layer overlying a substrate; depositing a layer of hydrogen silsesquioxane (HSQ) filling the gaps; depositing a second dielectric layer on the first patterned conductive layer and on the HSQ gap fill layer; planarizing an upper surface of the second dielectric layer; forming a through-hole in the second dielectric layer exposing at least a portion of the upper surface of the first conductive feature, and exposing at least a portion of the HSQ gap fill layer; vacuum baking to outgas impurities contained in the HSO gap fill layer; low pressure baking to drive off impurities contained in the HSQ gap fill layer; and filling the through-hole with a conductive material deposited on the barrier layer.
Claim 20
Dependent Claim
33 words
The method of claim 17, wherein the through-hole forming step includes exposing at least a portion of a side surface of the first conductive feature, the filling step comprising forming a borderless via.
Claim 21
Dependent Claim
30 words
The method of claim 17, wherein the step of depositing a barrier layer step comprises depositing titanium nitride on at least the exposed portions of the HSQ gap fill layer.
Claim 22
Independent Claim
43 words
The method of clam 17, wherein the low pressure baking step comprises: baking at a pressure of about 20 Torr to about 40 Torr for about 10 seconds to about 20 seconds at a temperature of about 445° C. to about 485° C.
Claim 23
Independent Claim
43 words
The method of clam 17, wherein the low pressure baking step comprises: baking at a pressure of about 20 Torr to about 40 Torr for about 10 seconds to about 20 seconds at a temperature of about 445° C. to about 485° C.
Claim 24
Dependent Claim
20 words
The method of claim 20, wherein the vacuum baking step comprises baking at a temperature of less than 445° C.
Claim 25
Dependent Claim
25 words
The method of claim 17, wherein the first patterned conductive layer comprises a metal layer and the first conductive feature comprises a first metal feature.
Claim 26
Dependent Claim
36 words
The method of claim 22, wherein the metal layer is a composite metal layer comprising: a lower refractory metal layer; an intermediate primary conductive layer comprising aluminum or an aluminum alloy; and an upper anti-reflective coating.
Claim 27
Dependent Claim
30 words
The method of claim 23, wherein the metal layer comprises a plurality of metal lines having a size no greater than about 0.25 microns, and the gaps comprise interwiring spacings.
Claim 28
Dependent Claim
23 words
The method of claim 17, wherein the low pressure baking step comprises baking at a temperature of about 445° C. to 485° C.
Claim 29
Dependent Claim
24 words
The method of claim 25, wherein the low pressure baking step and the conductive material filling step are performed at substantially the same temperatures.
Claim 30
Dependent Claim
29 words
The method of claim 26, wherein the low pressure baking step further comprises baking at a pressure of about 20 Torr for about 10 seconds to about 20 seconds.
Claim 31
Dependent Claim
25 words
The method of claim 25, wherein the low pressure baking step further comprises baking at a pressure of about 20 Torr to about 40 Torr.
Claim 32
Dependent Claim
36 words
The method of claim 28, wherein the low pressure baking step further comprises baking for about 10 seconds to about 20 seconds at a pressure of about 20 Torr and a temperature of about 445° C.
Claim 33
Dependent Claim
33 words
The method of claim 17, wherein no intervening wet or thermal processing is performed between the low pressure baking and filling the through-hole with the conductive material stress to form the borderless via.
Claim 34
Dependent Claim
24 words
The method of claim 17, wherein the low pressure baking step and the conductive material filling step are performed in the same reaction chamber.
Claim 35
Dependent Claim
33 words
The method of claim 17, wherein the vacuum baking step comprises vacuum baking at a first temperature, and the low-pressure baking step comprises baking at a second temperature higher than the first temperature.
Claim 36
Dependent Claim
30 words
The method of claim 32, wherein the step of low pressure baking is performed in the same tool employed for the step of filling the through-hole with the conductive material.
References Cited (Backward Citations)
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