Patent US6044025A successfully refreshed from Google Patents.
US6044025A
Expired / Lapsed
US
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PROM with built-in JTAG capability for configuring FPGAs
Assignee: Xilinx Inc
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Filing: 1999-02-04
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Granted: 2000-03-28
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Expires: 2019-02-04
Abstract
Abstract The invention provides a structure and method for configuring an FPGA from a PROM using a boundary scan chain. A PROM is provided that comprises JTAG circuitry. Configuration data is stored in the PROM memory as in known PROMs. When the data is retrieved from the PROM memory it is provided on a standard JTAG Test Access Port (TAP). The JTAG-compatible PROM is included as part of a JTAG scan chain, preferably directly preceding the FPGA to be configured by the PROM. The PROM can be controlled either externally or via JTAG commands received down the scan chain. Therefore, a reconfiguration of the FPGA can be initiated via standard JTAG commands. In one embodiment, the PROM itself is programmed with the FPGA configuration data using the JTAG TAP port.
Inventors
- 👤 Gary R. Lawman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:23
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R31/318519; G06; G06F; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
104 words
A programmable read-only memory (PROM) for configuring a field programmable gate array (FPGA) through boundary scan, comprising: a PROM memory array for storing user configuration data for the FPGA; and a JTAG test port comprising a test data input (TDI) pin, a test data output (TDO) pin, a test clock pin (TCK), a test mode (TMS) pin, and a control circuit; wherein the JTAG test port is coupled to receive JTAG instructions from the TDI, TCK, and TMS pins, to receive the data from the memory, and to provide the data to the TDO pin, whereby the data is used to configure the FPGA.
Claim 2
Dependent Claim
104 words
A programmable read-only memory (PROM) for configuring a field programmable gate array (FPGA) through boundary scan, comprising: a PROM memory array for storing user configuration data for the FPGA; and a JTAG test port comprising a test data input (TDI) pin, a test data output (TDO) pin, a test clock pin (TCK), a test mode (TMS) pin, and a control circuit; wherein the JTAG test port is coupled to receive JTAG instructions from the TDI, TCK, and TMS pins, to receive the data from the memory, and to provide the data to the TDO pin, whereby the data is used to configure the FPGA.
Claim 3
Dependent Claim
31 words
The PROM of claim 1, wherein the JTAG test port is further coupled to receive the data from the TDI pin and to provide the data to the PROM memory array.
Claim 4
Dependent Claim
22 words
The PROM of claim 2, wherein the PROM supports a JTAG verify command for verifying the data in the PROM memory array.
Claim 5
Dependent Claim
170 words
A structure for configuring a field programmable gate array (FPGA) from a programmable read-only memory (PROM) through boundary scan, comprising: a PROM having a PROM memory array for storing user configuration data for the FPGA, and further having a JTAG test port comprising a test data input pin, a test data output pin, a test clock pin, a test mode pin, and a control circuit; and an FPGA having a JTAG test port comprising a test data input pin, a test data output pin, a test clock pin, a test mode pin, and a control circuit, the FPGA test data input pin being coupled to the PROM test data output pin to form a boundary scan chain; wherein the PROM JTAG test port has a test mode in which the PROM is transparent to the boundary scan chain, and further has a configuration mode in which the PROM is used to configure the FPGA with the user configuration data stored in the PROM memory array through the boundary scan chain.
Claim 6
Dependent Claim
170 words
A structure for configuring a field programmable gate array (FPGA) from a programmable read-only memory (PROM) through boundary scan, comprising: a PROM having a PROM memory array for storing user configuration data for the FPGA, and further having a JTAG test port comprising a test data input pin, a test data output pin, a test clock pin, a test mode pin, and a control circuit; and an FPGA having a JTAG test port comprising a test data input pin, a test data output pin, a test clock pin, a test mode pin, and a control circuit, the FPGA test data input pin being coupled to the PROM test data output pin to form a boundary scan chain; wherein the PROM JTAG test port has a test mode in which the PROM is transparent to the boundary scan chain, and further has a configuration mode in which the PROM is used to configure the FPGA with the user configuration data stored in the PROM memory array through the boundary scan chain.
Claim 7
Dependent Claim
29 words
The structure of claim 4, wherein the PROM JTAG test port is coupled to program the PROM memory array with the user configuration data through the boundary scan chain.
Claim 8
Dependent Claim
19 words
The structure of claim 5, wherein the PROM supports a JTAG verify command for verifying the user configuration data.
Claim 9
Dependent Claim
17 words
The structure of claim 4, wherein the PROM directly precedes the FPGA in the boundary scan chain.
Claim 10
Independent Claim
81 words
A method to configure a field programmable gate array (FPGA) from a programmable read-only memory (PROM) through boundary scan, the PROM comprising a PROM memory array storing configuration data for the FPGA, the method comprising: forming a boundary scan chain with the PROM and the FPGA in which the PROM precedes the FPGA; placing the PROM in configuration mode; and loading the configuration data stored in the PROM memory array into the FPGA from the PROM through the boundary scan chain.
Claim 11
Independent Claim
81 words
A method to configure a field programmable gate array (FPGA) from a programmable read-only memory (PROM) through boundary scan, the PROM comprising a PROM memory array storing configuration data for the FPGA, the method comprising: forming a boundary scan chain with the PROM and the FPGA in which the PROM precedes the FPGA; placing the PROM in configuration mode; and loading the configuration data stored in the PROM memory array into the FPGA from the PROM through the boundary scan chain.
Claim 12
Dependent Claim
24 words
The method of claim 8, further comprising: loading the configuration data for the FPGA into the PROM memory array through the boundary scan chain.
Claim 13
Dependent Claim
21 words
The method of claim 9, further comprising: reading back the configuration data through the boundary scan chain to verify the data.
Claim 14
Dependent Claim
17 words
The method of claim 8, wherein the PROM directly precedes the FPGA in the boundary scan chain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-28 | 2003-09-27 | 2004-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-28 | 2007-09-27 | 2008-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-28 | 2011-09-27 | 2012-03-28 | $7700.00 | Window Closed / Lapsed |