Clock signal control apparatus for data output buffer

Claim 2

A data output buffer apparatus, comprising: a clock signal generator that receives a first clock signal and generates a second clock signal having a period based on a period of the first clock signal, wherein the clock signal generator comprises, a generator that generates a plurality of intermediate clock signals based on a period of the first clock signal, and a delay controller that delays the first clock signal based on the plurality of intermediate clock signals to output the second clock signal; a clock signal controller that delays the second clock signal from the clock signal generator for a predetermined time to generate a third clock signal and an output enable signal; and a data output buffer that receives a data signal and buffers the data signal based on the third clock signal and the output enable signal to generate an output signal.

Claim 3

The apparatus of claim 1, wherein the generator comprises: a clock signal divider that divides a frequency of the first clock signal; and a period comparator that detects a period of an output signal from the clock signal divider and generates the plurality of intermediate clock signals based on the detected output signal period of the clock signal divider.

Claim 4

The apparatus of claim 2, wherein the period comparator comprises: a first delay unit that delays the output signal from the clock signal divider; a second delay unit that delays an output signal from the first delay unit; a third delay unit that delays an output signal from the second delay unit; an inverter unit that inverts the output signal from the clock signal divider; a first latch unit that latches an output signal from the first delay unit based on an output signal from the inverter unit to output a first intermediate clock signal of the plurality of intermediate clock signals; a second latch unit that latches an output signal from the second delay unit based on the output signal from the inverter unit to output the a second intermediate clock signal; and a third latch unit that latches an output signal from the third delay unit based on the output signal from the inverter unit to output a third intermediate clock signal.

Claim 5

The apparatus of claim 3, wherein the first latch unit receives the output signal from the first delay unit through a first pair of inverters coupled in series, the second latch unit receives the output signal from the second delay unit through a second pair of inverters coupled in series, and the third latch unit receives the output signal from the third delay unit through a third pair of inverters coupled in series.

Claim 6

The apparatus of claim 3, wherein each of the first through third delay units comprise: a pair of inverters coupled in series to sequentially invert an inputted clock signal; a first delay element that delays an output signal from the pair of series inverters; a first logic-gate that logically processes an output signal from the first delay element and the inputted clock signal; an inverter that inverts an output signal from the first logic-gate; a second delay element that delays an output signal from the inverter; and a second logic-gate for that logically processes an output signal from the second delay element and the inputted clock signal.

Claim 7

The apparatus of claim 5, wherein the first and second logic-gates are NAND-gates, and wherein each of the first through third latch units is a flip-flop circuit.

Claim 8

The apparatus of claim 2, wherein the delay controller comprises: a negative delay unit that negatively delays the first clock signal; first and second delay units that sequentially delay the first clock signal; first transmission circuit that switches an output signal from the negative delay unit to output the second clock signal; a second transmission circuit that switches the first clock signal to output the second clock signal; a third transmission circuit that switches an output signal from the first delay unit to output the second clock signal; and a fourth transmission circuit that switches an output signal from the second delay unit to output the second clock signal.

Claim 9

The apparatus of claim 7, wherein the delay controller comprises an inverter for inverting one of the plurality of intermediate clock signals to output an enable signal to the negative delay unit.

Claim 10

The apparatus of claim 7, wherein the delay controller comprises: a first inverter that inverts a first intermediate clock signal from the period comparator and applies the inverted signal to the first transmission circuit; a second inverter that inverts a second intermediate clock signal from the period comparator; a first logic-gate for logically processing an output signal from the second inverter and the first intermediate clock signal and applying an output signal to the second transmission circuit; a third inverter that inverts the output signal from the first logic-gate and applies the inverted signal to the second transmission circuit; a fourth inverter that inverts a third intermediate clock signal from the period comparator and applies the inverted signal to the fourth transmission circuit; a second logic-gate for logically processing an inverse third intermediate clock signal and the second intermediate clock signal and applying an output signal to the third transmission circuit; and a fifth inverter that inverts the output signal from the second logic-gate and applies the inverted signal to the third transmission circuit.

Claim 11

The apparatus of claim 9, wherein each of the transmission circuits comprise a transmission gate, and wherein the first and second logic-gates are NAND-gates.

Claim 12

A clock signal control apparatus for a data output buffer that includes an output buffer to buffer an input data, comprising: a clock signal generator that receives a first clock signal and generates a plurality of second clock signals having a period based on a period of the first clock signal, wherein the clock signal generator delays the first clock signal based on each of the plurality of second clock signals to generate a plurality of delayed first clock signals, and wherein a selected one of the delayed first clock signals is output as a third clock signal; and a clock signal controller that delays the third clock signal for a predetermined time to generate a fourth clock signal and an output enable signal.

Claim 13

A clock signal control apparatus for a data output buffer that includes an output buffer to buffer an input data, comprising: a clock signal generator that receives a first clock signal and generates a plurality of second clock signals having a period based on a period of the first clock signal, wherein the clock signal generator delays the first clock signal based on each of the plurality of second clock signals to generate a plurality of delayed first clock signals, and wherein a selected one of the delayed first clock signals is output as a third clock signal; and a clock signal controller that delays the third clock signal for a predetermined time to generate a fourth clock signal and an output enable signal.

Claim 14

The apparatus of claim 11, wherein the output buffer receives the input data and buffers the input data based on the fourth clock signal and the output enable signal to generate an output signal.

Claim 15

The apparatus of claim 11, wherein the clock signal generator comprises: a clock signal divider that divides a frequency of the first clock signal; and a period comparator that detects a period of an output signal from the clock signal divider and generates the plurality of second clock signals based on the detected output signal period of the clock signal divider.

Claim 16

The apparatus of claim 13, wherein the period comparator comprises: a plurality of delay units that delay an output signal from the clock signal divider; an inverter unit that inverts the output signal from the clock signal divider; a plurality of latch units that latch a corresponding output from a corresponding one of the plurality of delay units based on an output signal from the inverter unit to output one of the plurality of second clock signals.

Claim 17

The apparatus of claim 14, wherein each of the plurality of delay units has a different delay period.

Claim 18

The apparatus of claim 13, wherein the clock signal generator further comprises a delay controller comprising: a negative delay unit that negatively delays the first clock signal; first and second delay units that sequentially delay the first clock signal; a plurality of transmission gates that transmit a corresponding one of at least the first clock signal, an output signal from the negative delay unit, an output signal from the first delay unit, an output signal from the second delay unit to output the third clock signal.

Claim 19

A data output buffer apparatus, comprising: a clock signal generator that receives a first clock signal and comprises a clock signal divider that divides a frequency of the first clock signal to generate a divided first clock signal, and wherein the clock signal generator generates a second clock signal based on a selected one of a plurality of variable width pulse signals based on the divided first clock signal; a clock signal controller that delays the second clock signal from the clock signal generator for a predetermined time to generate a third clock signal and an output enable signal; and a data output buffer that receives a data signal and buffers the data signal based on the third clock signal and the output enable signal to generate an output signal.

Claim 20

A data output buffer apparatus, comprising: a clock signal generator that receives a first clock signal and comprises a clock signal divider that divides a frequency of the first clock signal to generate a divided first clock signal, and wherein the clock signal generator generates a second clock signal based on a selected one of a plurality of variable width pulse signals based on the divided first clock signal; a clock signal controller that delays the second clock signal from the clock signal generator for a predetermined time to generate a third clock signal and an output enable signal; and a data output buffer that receives a data signal and buffers the data signal based on the third clock signal and the output enable signal to generate an output signal.

Claim 21

The apparatus of claim 17, wherein the clock signal generator comprises: a period comparator that detects a period of the divided first clock signal from the clock signal divider and generates the plurality of variable width pulse signals based on the detected period of the divided first clock signal.

Claim 22

The apparatus of claim 18, wherein the clock signal generator further comprises a delay controller that modifies the first clock signal based on the plurality of variable width pulse signals from the period comparator to output the second clock signal to the clock signal controller.

Claim 23

The apparatus of claim 19, wherein a maintaining time of the output signal increases as a frequency of the first clock signal decreases, and wherein a data access time decreases as the frequency of the first clock signal increases.