Management process for electrical energy storage battery systemsand control arrangement for application of the process

Claim 2

A management process for systems made up of cells electrically connected in series that each include one or more electrical energy storage battery units to form a system for subjection to alternating charge and discharge phases in which each cell is associated with an individual current bypass circuit connected to terminals of said cell and controlled by a controller operating in accordance with indications supplied by a circuit measuring at least one parameter of said cell, said process comprising the steps of: measuring the parameter of each of the cells of the system; and providing cell by cell balancing of the system based on said measurements, wherein balancing is initiated at any time over a time period that covers all operating phases of said system when said system is supplying power to an application, and is provided both during battery charge phases and during idle phases between charging and discharging of said application.

Claim 3

The measurement process according to claim 1, wherein said measured parameter is a voltage or temperature of said cells.

Claim 4

A control arrangement for a battery storage system including a plurality of cells connected in series comprising: a plurality of common modules, each common module including a measurement circuit measuring a cell current; a bypass circuit connected in parallel to one of the plurality of cells providing the cell with a particular state of charge; a controller controlling said bypass circuit and said measurement circuit based on received control signals; a measurement transducer for receiving measurement indications from said measurement circuits, converting them, and transmitting them; a common control logic including an input interface for receiving said transmitted measured cell currents, determining if plurality of cells are electrically balanced a cell; and an output interface for transmitting signals to control said common module controllers based on said measured currents, wherein said common control logic operates over a time period covering charge phases and idle phases.

Claim 5

A control arrangement for a battery storage system including a plurality of cells connected in series comprising: a plurality of common modules, each common module including a measurement circuit measuring a cell current; a bypass circuit connected in parallel to one of the plurality of cells providing the cell with a particular state of charge; a controller controlling said bypass circuit and said measurement circuit based on received control signals; a measurement transducer for receiving measurement indications from said measurement circuits, converting them, and transmitting them; a common control logic including an input interface for receiving said transmitted measured cell currents, determining if plurality of cells are electrically balanced a cell; and an output interface for transmitting signals to control said common module controllers based on said measured currents, wherein said common control logic operates over a time period covering charge phases and idle phases.

Claim 6

The control arrangement of claim 3, wherein said common control logic further comprises supervisor logic for supervising said cells for charge balancing of the cells by repeated interrogation of said individual measurement circuits, obtaining said measurement indications, processing said measurement indications, and transmitting said control signals based on said processed measurement indications.

Claim 7

The control arrangement of claim 4, wherein said common control logic further comprises a processor for determining addresses for said control signals to alternate the switching on and off of said bypass circuit connected to a given cell based on said measurement indications from one preceding balancing phase for said given cell.

Claim 8

The control arrangement of claim 5, wherein said control logic further comprises a processor for determining the balancing time per cell after appearance of an imbalance determined by said common control logic from measurement indications supplied by said measurement circuits.

Claim 9

The control arrangement of claim 6, wherein said control logic further comprises a processor for calculating a characteristic capacity value for each cell according to the time for charging that cell and the charging current successively chosen so that said balancing takes account of any capacity differences between cells.

Claim 10

The control arrangement of claim 4, wherein said common control logic further comprises: a memory storing at least one value characteristic of the optimal electrical state of each cell of said system; a processor for calculating at least one characteristic electrical state threshold value for each characteristic optimal state value; and a comparator for comparing values corresponding to said measurement indications to said at least one characteristic electrical threshold value.

Claim 11

The control arrangement of claim 3 wherein said controller further comprises a discriminator for distinguishing functions attributed to the various control pulses sent by the common control logic.

Claim 12

The control arrangement of claim 3, wherein said measurement circuit supplies a measurement signal under control of said controller on receipt of a predetermined control pulse at a predetermined location in the stream of control pulses.

Claim 13

A control arrangement for a plurality of cells connected in series comprising: a plurality of measurement circuits each associated with one of said plurality of cells for measuring said one cell's current; a plurality of bypass circuits each connected in parallel to one of said plurality of cells providing said one cell with a particular state of charge; a plurality of controllers each for controlling one of said plurality of bypass circuits and measurement circuits based on received control signals; and a common control logic including an input interface for receiving said measured cell currents, a processor for determining if the plurality of cells are electrically balanced; and an output interface for transmitting signals to control said controllers based on said measured cell currents, wherein said common control logic operates over a time period covering charge phases and idle phases.

Claim 14

A control arrangement for a plurality of cells connected in series comprising: a plurality of measurement circuits each associated with one of said plurality of cells for measuring said one cell's current; a plurality of bypass circuits each connected in parallel to one of said plurality of cells providing said one cell with a particular state of charge; a plurality of controllers each for controlling one of said plurality of bypass circuits and measurement circuits based on received control signals; and a common control logic including an input interface for receiving said measured cell currents, a processor for determining if the plurality of cells are electrically balanced; and an output interface for transmitting signals to control said controllers based on said measured cell currents, wherein said common control logic operates over a time period covering charge phases and idle phases.

Claim 15

The control arrangement of claim 11, wherein said common control logic further comprises supervisor logic for supervising said cells for charge balancing of the cells by repeated interrogation of said individual measurement circuits, obtaining said measurement indications, processing said measurement indications, and transmitting said control signals based on said processed measurement indications.

Claim 16

The control arrangement of claim 12, wherein said common control logic further comprises: a memory storing at least one value characteristic of the optimal electrical state of each cell of said system; a processor for calculating at least one characteristic electrical state threshold value for each characteristic optimal state value; and a comparator for comparing values corresponding to said measurement indications to said at least one characteristic electrical threshold value.

Claim 17

The control arrangement of claim 12, wherein said common control logic further comprises a processor for determining addresses for said control signals to alternated the switching on and off of said bypass circuit connected to a given cell based on said measurement indications from one preceding balancing phase for said given cell.

Claim 18

The control arrangement of claim 14, wherein said control logic further comprises a processor for determining the balancing time per cell after appearance of an imbalance determined by said common control logic from measurement indications supplied by said measurement circuits.

Claim 19

The control arrangement of claim 15, wherein said control logic further comprises a processor for calculating a characteristic capacity value for each cell according to the time for charging that cell and the charging current successively chosen so that said balancing takes account of any capacity differences between cells.

Claim 20

The control arrangement of claim 11 wherein said controller further comprises a discriminator for distinguishing functions attributed to the various control pulses sent by the common control logic.

Claim 21

The control arrangement of claim 11, wherein said measurement circuit supplies a measurement signal under control of said controller on receipt of a predetermined control pulse at a predetermined location in the stream of control pulses.

Claim 22

A control arrangement for a battery storage system including a plurality of cells connected in series comprising: a plurality of common modules, each common module including a measurement circuit measuring a cell current; a bypass circuit connected in parallel to one of the plurality of cells providing the cell with a particular state of charge; a controller controlling said bypass circuit and said measurement circuit based on received control signals; a measurement transducer for receiving measurement indications from said measurement circuits, converting them, and transmitting them; a common control logic including an input interface for receiving said transmitted measured cell currents, determining if plurality of cells are electrically balanced a cell; and an output interface for transmitting signals to control said common module controllers based on said measured currents, wherein said plurality of common module controllers are connected in serial communication with each other, said common module controllers including a first controller connected to said common control logic output interface for receiving said control pulses addressed to said first controller and forwarding control pulses addressed to other controllers.

Claim 23

A control arrangement for a battery storage system including a plurality of cells connected in series comprising: a plurality of common modules, each common module including a measurement circuit measuring a cell current; a bypass circuit connected in parallel to one of the plurality of cells providing the cell with a particular state of charge; a controller controlling said bypass circuit and said measurement circuit based on received control signals; a measurement transducer for receiving measurement indications from said measurement circuits, converting them, and transmitting them; a common control logic including an input interface for receiving said transmitted measured cell currents, determining if plurality of cells are electrically balanced a cell; and an output interface for transmitting signals to control said common module controllers based on said measured currents, wherein said plurality of common module controllers are connected in serial communication with each other, said common module controllers including a first controller connected to said common control logic output interface for receiving said control pulses addressed to said first controller and forwarding control pulses addressed to other controllers.

Claim 24

A control arrangement for a plurality of cells connected in series comprising: a plurality of measurement circuits each associated with one of said plurality of cells for measuring said one cell's current; a plurality of bypass circuits each connected in parallel to one of said plurality of cells providing said one cell with a particular state of charge; a plurality of controllers each for controlling one of said plurality of bypass circuits and measurement circuits based on received control signals; and a common control logic including an input interface for receiving said measured cell currents, a processor for determining if the plurality of cells are electrically balanced; and an output interface for transmitting signals to control said controllers based on said measured cell currents, wherein said plurality of common module controllers are connected in serial communication with each other, said common module controllers including a first controller connected to said common control logic output interface for receiving said control pulses addressed to said first controller and forwarding control pulses addressed to other controllers.

Claim 25

A control arrangement for a plurality of cells connected in series comprising: a plurality of measurement circuits each associated with one of said plurality of cells for measuring said one cell's current; a plurality of bypass circuits each connected in parallel to one of said plurality of cells providing said one cell with a particular state of charge; a plurality of controllers each for controlling one of said plurality of bypass circuits and measurement circuits based on received control signals; and a common control logic including an input interface for receiving said measured cell currents, a processor for determining if the plurality of cells are electrically balanced; and an output interface for transmitting signals to control said controllers based on said measured cell currents, wherein said plurality of common module controllers are connected in serial communication with each other, said common module controllers including a first controller connected to said common control logic output interface for receiving said control pulses addressed to said first controller and forwarding control pulses addressed to other controllers.