Booster circuit and semiconductor memory device having the same

Claim 2

A booster circuit comprising: a booster unit having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit, and having a gate supplied with an inverted signal of a signal supplied to the signal input terminal of the booster unit.

Claim 3

A booster circuit comprising: a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage.

Claim 4

A booster circuit comprising: a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage.

Claim 5

The booster circuit according to claim 2, wherein the MOS transistor is turned off when the booster unit at the first stage operates.

Claim 6

The booster circuit according to claim 2, further comprising: a detector circuit for comparing a voltage value of the voltage output terminal of the booster unit at a last stage with a preset value, and for outputting an oscillator circuit activation signal in accordance with a comparison result; and an oscillator circuit for generating the signal to be supplied to each of the signal input terminals of the plurality of booster units, in accordance with the oscillator circuit activation signal.

Claim 7

The booster circuit according to claim 2, wherein the MOS transistor is of an intrinsic type.

Claim 8

The booster circuit according to claim 2, wherein each of the booster units includes: a MOS transistor having a current path and a gate, connected such that an end of the current path and the gate are connected to the voltage input terminal and such that another end of the current path is connected to the voltage output terminal; and a capacitor being connected to the voltage input terminal and the signal input terminal.

Claim 9

The booster circuit according to claim 6, wherein the MOS transistors included in the booster units are of an intrinsic type.

Claim 10

A booster circuit comprising: a booster unit having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit, and having a gate supplied with a signal based on an inverted signal of a signal supplied to the signal input terminal of the booster unit.

Claim 11

A booster circuit comprising: a booster unit having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit, and having a gate supplied with a signal based on an inverted signal of a signal supplied to the signal input terminal of the booster unit.

Claim 12

A booster circuit comprising: a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with a signal based on an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage.

Claim 13

A booster circuit comprising: a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage; and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with a signal based on an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage.

Claim 14

The booster circuit according to claim 9, wherein the MOS transistor is turned off when the booster unit at the first stage operates.

Claim 15

The booster circuit according to claim 9, further comprising: a detector circuit for comparing a voltage value of the voltage output terminal of the booster unit at a last stage with a preset value, and for outputting an oscillator circuit activation signal in accordance with a comparison result and the booster circuit activation signal; and an oscillator circuit for generating the signal to be supplied to each of the signal input terminals of the plurality of booster units, in accordance with the oscillator circuit activation signal and the booster circuit activation signal.

Claim 16

The booster circuit according to claim 9, wherein the MOS transistor is of an intrinsic type.

Claim 17

The booster circuit according to claim 9, wherein each of the booster units includes: a MOS transistor having a current path and a gate, connected such that an end of the current path and the gate are connected to the voltage input terminal and such that another end of the current path is connected to the voltage output terminal; and a capacitor being connected to the voltage input terminal and the signal input terminal.

Claim 18

The booster circuit according to claim 13, wherein the MOS transistors included in the booster units are of an intrinsic type.

Claim 19

A semiconductor memory device comprising: a booster circuit including a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage, and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage or supplied with a signal based on the inverted signal; a reference voltage generator circuit for generating a reference voltage; and an internal voltage generator circuit for generating a voltage to be supplied to a memory cell from a boosted voltage obtained through the voltage output terminal of the booster unit at a last stage, with reference to the reference voltage.

Claim 20

A semiconductor memory device comprising: a booster circuit including a plurality of booster units each having a voltage input terminal, a voltage output terminal, and a signal input terminal connected to said voltage input terminal, and connected in series to form a plurality of stages, respectively, such that the voltage input terminal of the booster unit at a present stage is connected to the voltage output terminal of the booster unit at a preceding stage and such that the signal input terminal of the booster unit at the present stage is supplied with an inverted signal of a signal supplied with the signal input terminal of the booster unit at the preceding stage, and a MOS transistor having a current path having a first terminal supplied with a power supply voltage and a second terminal connected to the voltage input terminal of the booster unit at a first stage, and having a gate supplied with an inverted signal of a signal supplied to the signal input terminal of the booster unit at the first stage or supplied with a signal based on the inverted signal; a reference voltage generator circuit for generating a reference voltage; and an internal voltage generator circuit for generating a voltage to be supplied to a memory cell from a boosted voltage obtained through the voltage output terminal of the booster unit at a last stage, with reference to the reference voltage.

Claim 21

The semiconductor memory device according to claim 15, wherein the booster circuit further includes a detector circuit for comparing a voltage value of the voltage output terminal of the booster unit at the last stage with a preset value, and for outputting an oscillator activation signal in accordance with a comparison result; and an oscillator circuit for generating the signal to be supplied to each of the signal input terminals of the plurality of booster units, in accordance with the oscillator circuit activation signal.

Claim 22

The semiconductor memory device according to claim 16, wherein the detector circuit compares the voltage value of the voltage output terminal of the booster unit at the last stage with the preset value, and outputs the oscillator circuit activation signal in accordance with the comparison result and the booster circuit activation signal.

Claim 23

The semiconductor memory device according to claim 17, wherein the oscillator circuit generates the signal to be supplied to each of the signal input terminals of the plurality of booster units, in accordance with the oscillator circuit activation signal and the booster circuit activation signal.

Claim 24

The semiconductor memory device according to claim 15, wherein each of the booster units includes: a MOS transistor having a current path and a gate, connected such that an end of the current path and the gate are connected to the voltage input terminal and such that another end of the current path is connected tithe voltage output terminal; and a capacitor being connected to the voltage input terminal and the signal input terminal.

Claim 25

The semiconductor memory device according to claim 19, wherein the n-type MOS transistors included in the booster units are of an intrinsic type.

Claim 26

The booster circuit according to claim 1, wherein the MOS transistor is an n-type MOS transistor.

Claim 27

The booster circuit according to claim 2, wherein the MOS transistor is an n-type MOS transistor.

Claim 28

The booster circuit according to claim 8, wherein the MOS transistor is an n-type MOS transistor.

Claim 29

The booster circuit according to claim 8, wherein the signal based on the inverted signal is an AND signal of a booster circuit activation signal and the inverted signal.

Claim 30

The booster circuit according to claim 9, wherein the MOS transistor is an n-type MOS transistor.

Claim 31

The booster circuit of according to claim 9, wherein the signal based on the inverted signal is an AND signal of a booster circuit activation signal and the inverted signal.

Claim 32

The semiconductor memory device according to claim 15, wherein the MOS transistor is an n-type MOS transistor.

Claim 33

The semiconductor memory device according to claim 15, wherein the signal based on the inverted signal is an AND signal of a booster circuit activation signal and the inverted signal.

Claim 34

A booster circuit comprising: a power supply terminal to which a power supply voltage is supplied; a booster unit having a transistor and a capacitor, the transistor having a current path and a gate electrode connected to a first end of the current path, the capacitor having a first electrode and a second electrode, the first electrode of the capacitor being connected to the first end of the current path of the transistor, a control signal being supplied to the second electrode of the capacitor, a signal differing in level from the power supply voltage being output from a second end of the current path of the transistor; and a circuit having a first terminal and a second terminal, the first terminal being connected to the power supply terminal, the second terminal being connected to the first end of the current path of the transistor, the circuit being controlled such that a leakage current from the first electrode of the capacitor to the power supply terminal is suppressed while the control signal is set at a predetermined level.

Claim 35

A booster circuit comprising: a power supply terminal to which a power supply voltage is supplied; a booster unit having a transistor and a capacitor, the transistor having a current path and a gate electrode connected to a first end of the current path, the capacitor having a first electrode and a second electrode, the first electrode of the capacitor being connected to the first end of the current path of the transistor, a control signal being supplied to the second electrode of the capacitor, a signal differing in level from the power supply voltage being output from a second end of the current path of the transistor; and a circuit having a first terminal and a second terminal, the first terminal being connected to the power supply terminal, the second terminal being connected to the first end of the current path of the transistor, the circuit being controlled such that a leakage current from the first electrode of the capacitor to the power supply terminal is suppressed while the control signal is set at a predetermined level.

Claim 36

The booster circuit according to claim 29, wherein the transistor is an n-type MOS transistor.

Claim 37

The booster circuit according to claim 29, wherein the circuit is constituted by an n-type MOS transistor.

Claim 38

A booster circuit comprising: a power supply terminal to which a power supply voltage is applied; a booster unit having a first transistor and a capacitor, the first transistor having a current path and a gate electrode connected to a first end of the current path, the capacitor having a first electrode and a second electrode, the first electrode of the capacitor being connected to the first end of the current path of the first transistor, a first control signal being supplied to the second electrode of the capacitor, a signal differing in level from the power supply voltage being output from a second end of the current path of the first transistor; and a second transistor having a first terminal, a second terminal, a gate terminal and a back gate terminal, the power supply terminal being connected to the first terminal, the second terminal being connected to the first terminal end of the current path of the first transistor, a signal based on at least a complimentary signal of the first control signal being supplied to the gate terminal.

Claim 39

A booster circuit comprising: a power supply terminal to which a power supply voltage is applied; a booster unit having a first transistor and a capacitor, the first transistor having a current path and a gate electrode connected to a first end of the current path, the capacitor having a first electrode and a second electrode, the first electrode of the capacitor being connected to the first end of the current path of the first transistor, a first control signal being supplied to the second electrode of the capacitor, a signal differing in level from the power supply voltage being output from a second end of the current path of the first transistor; and a second transistor having a first terminal, a second terminal, a gate terminal and a back gate terminal, the power supply terminal being connected to the first terminal, the second terminal being connected to the first terminal end of the current path of the first transistor, a signal based on at least a complimentary signal of the first control signal being supplied to the gate terminal.

Claim 40

The booster circuit according to claim 32, wherein a ground potential is supplied to the back gate terminal.

Claim 41

The booster circuit according to claim 32, wherein the complimentary signal of the first control signal is supplied to the gate terminal.

Claim 42

The booster circuit according to claim 32, wherein the complimentary signal of the first control signal and a second control signal are supplied to the gate terminal.

Claim 43

The booster circuit according to claim 32, wherein the first transistor is an n-type MOS transistor.

Claim 44

The booster circuit according to claim 32, wherein the second transistor is an n-type MOS transistor.