Method and apparatus for removal of VT drop in the output diode of charge pumps

Claim 2

A charge pump circuit, comprising: a first stage configured to receive a first clock signal; a second stage coupled to said first stage, said second stage configured to receive a second clock signal; and an output diode coupled to said second stage, said output diode including a first switch circuit coupled to a first bootstrapping circuit, said first bootstrapping circuit configured to receive a first and a second non-overlapping clock signal.

Claim 3

The charge pump circuit of claim 1, wherein said charge pump further comprises a first intermediate stage and a second intermediate stage, said first intermediate stage is coupled between said first stage and said second intermediate stage, said first intermediate stage is configured to receive said second clock signal, said second intermediate stage is coupled between said first intermediate stage and said second stage, said second intermediate stage is configured to receive said first clock signal.

Claim 4

The charge pump of claim 1, wherein said first switch circuit includes a first terminal coupled to an input of said output diode, a second terminal coupled to an output of said output diode, and a control terminal.

Claim 5

The charge pump of claim 3, wherein said bootstrapping circuit is coupled between said first terminal of said first switch circuit and said control terminal of said first switch circuit, said bootstrapping circuit further comprises: a first capacitive device configured to receive said first non-overlapping clock signal; a second capacitive device configured to receive said second non-overlapping clock signal; a second switch circuit having a first terminal coupled to said first terminal of said first switch circuit, a second terminal coupled to said control terminal of said first switch circuit, and a control terminal coupled to said first capacitive device; and a third switch circuit having a first terminal coupled to said first terminal of said first switch circuit, a second terminal coupled to said control terminal of said second switch circuit, and a control terminal coupled to said second capacitive device.

Claim 6

The charge pump of claim 4, wherein said first switch circuit, said second switch circuit, and said third switch circuits are n-channel MOS transistors.

Claim 7

The charge pump of claim 5, wherein said first switch circuit is larger in size than said second switch circuit and said third switch circuit.

Claim 8

The charge pump of claim 4, wherein said first switch circuit, said second switch circuit, and said third switch circuit are p-channel MOS transistors.

Claim 9

The charge pump of claim 7, wherein said first switch circuit is larger in size than said second switch circuit and said third switch circuit.

Claim 10

The charge pump of claim 1, wherein said first and said second non-overlapping clock signals do not have logic high voltage signals at the same time.

Claim 11

The charge pump of claim 9, wherein said first non-overlapping clock signal transitions to a logic low voltage level a first duration before said second non-overlapping clock signal transitions to a logic high voltage level, and said second non-overlapping clock signal transitions to said logic low voltage level a second duration before said first non-overlapping clock signal transitions to said logic high voltage level, said first duration and said second duration are greater than 0 seconds.

Claim 12

The charge pump of claim 10, wherein said second clock signal transitions to a logic high voltage level a third duration before said first non-overlapping clock signal transitions to logic low voltage level, and said first non-overlapping clock signal transitions to said logic high voltage level a fourth duration before said second clock signal transitions to said logic low voltage level, said third duration and said fourth duration are greater than 0 volts.

Claim 13

The charge pump of claim 1, wherein said first and said second non-overlapping clock signals do not have logic low voltage signals at the same time.

Claim 14

The charge pump of claim 12, wherein said first non-overlapping clock signal transitions to a logic high voltage level a first duration before said second non-overlapping clock signal transitions to a logic low clock signal, and said second non-overlapping clock signal transitions to said logic high voltage level a second duration before said first non-overlapping clock signal transitions to said logic low voltage level, said first duration and said second duration are greater than 0 seconds.

Claim 15

The charge pump of claim 13, wherein said second clock signal transitions to said logic low voltage level a third duration before said first non-overlapping clock signal transitions to said logic high voltage level, and said first non-overlapping clock signal transitions to said logic low voltage level a fourth duration before said second clock signal transitions to said logic high voltage level, said third and said fourth durations are greater than 0 seconds.

Claim 16

The charge pump of claim 1, wherein said first stage includes a first capacitive device and a first diode, said first capacitive device receives said first non-overlapping clock signal, said first diode includes a second switch circuit coupled to a second bootstrapping circuit, said second bootstrapping circuit is configured to receive said first and said second non-overlapping clock signals.

Claim 17

The charge pump of claim 15, wherein said second stage includes a second capacitive device and a second diode, said second capacitive device receives said second clock signal, said second diode includes a third switch circuit coupled to a third bootstrapping circuit, said third bootstrapping circuit is configured to receive said first and said second clock signals.

Claim 18

The charge pump of claim 16, wherein said first switch circuit in said output diode includes a first terminal coupled to an input of said output diode, a second terminal coupled to a n output of said output diode, and a control terminal, and wherein said first bootstrapping circuit is coupled between said first terminal of said first switch circuit and said control terminal of said first switch circuit, and wherein said second switch circuit in said first diode includes a first terminal coupled to an input of said first diode, a second terminal coupled to an output of said first diode, and a control terminal, and wherein said second bootstrapping circuit is coupled between said first terminal of said second switch circuit and said control terminal of said second switch circuit , and wherein said third switch circuit in said second diode includes a first terminal coupled to an input of said second diode, a second terminal coupled to an output of said second diode, and a control terminal, and wherein said third bootstrapping circuit is coupled between said first terminal of said third switch circuit and said control terminal of said third switch circuit.

Claim 19

The charge pump of claim 17, wherein said first bootstrapping circuit comprises: a third capacitive device configured to receive said first non-overlapping clock signal; a fourth capacitive device configured to receive said second non-overlapping clock signal; a fourth switch circuit having a first terminal coupled to said first terminal of said first switch device, a second terminal coupled to said control terminal of said first switch circuit, and a control terminal coupled to said third capacitive device; and a fifth switch circuit having a first terminal coupled to said first terminal of said first switch circuit, a second terminal coupled to said control terminal of said fourth switch circuit, and a control terminal coupled to said fourth capacitive device.

Claim 20

The charge pump of claim 18, wherein said second bootstrapping circuit comprises: a fifth capacitive device configured to receive said second clock signal; a sixth capacitive device configured to receive said first clock signal; a sixth switch circuit having a first terminal coupled to said first terminal of said second switch device, a second terminal coupled to said control terminal of said second switch circuit, and a control terminal coupled to said fifth capacitive device; and a seventh switch circuit having a first terminal coupled to said first terminal of said second switch circuit, a second terminal coupled to said control terminal of said sixth switch circuit, and a control terminal coupled to said sixth capacitive device.

Claim 21

The charge pump of claim 19, wherein said third bootstrapping circuit comprises: a seventh capacitive device configured to receive said first non-overlapping clock signal; a eighth capacitive device configured to receive said second non-overlapping clock signal; a eighth switch circuit having a first terminal coupled to said first terminal of said third switch device, a second terminal coupled to said control terminal of said third switch circuit, and a control terminal coupled to said seventh capacitive device; and a ninth switch circuit having a first terminal coupled to said first terminal of said third switch circuit, a second terminal coupled to said control terminal of said eighth switch circuit, and a control terminal coupled to said eighth capacitive device.

Claim 24

The method of claim 21, wherein said first voltage level, said second voltage level, and said third voltage level are at the same voltage level.

Claim 25

The method of claim 21, wherein step (d) includes the steps of: (1) transitioning said first non-overlapping clock signal to a logic low voltage level before said second non-overlapping clock signal transitions to a logic high voltage level; (2) transitioning said second non-overlapping clock signal to said logic low voltage level before said first non-overlapping clock signal transitions to said logic high voltage level; (3) transitioning said second clock signal to said logic high voltage level before said first non-overlapping clock signal transitions to said logic low voltage level; and (4) transitioning said second non-overlapping clock signal to said logic high voltage level before said second clock signal transitions to said logic low voltage level.

Claim 26

The method of claim 21, wherein step (d) includes the steps of: (1) transitioning said first non-overlapping clock signal to a logic high voltage level before said second non-overlapping clock signal transitions to a logic low voltage level; (2) transitioning said second non-overlapping clock signal to said logic high voltage level before said second non-overlapping clock signal transitions to said logic low voltage level; (3) transitioning said second clock signal to said logic low voltage level before said first non-overlapping clock signal transitions to said logic high voltage level; and (4) transitioning said first non-overlapping clock signal to said logic low voltage level before said second clock signal transitions to said logic high voltage level.