Image sensor having self-aligned silicide layer

Claim 2

A CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a photo-sensing region, in which a buried photodiode is formed, for sensing light from an object; a plurality of transistors electrically coupled to the buried photodiode; silicide layers formed on gates and heavily doped regions of said pluralit of transistors except the photo-sensing region; and a plurality of insulating layer patterns which are provided by patterning an insulating layer, wherein the insulating layer patterns include: insulating spacers formed on sidewalls of the gates, which are respectively provided for the plurality of transistors; and a passivation layer formed on the photo-sensing region and on a sidewall of neighboring one of the gates.

Claim 3

The CMOS image sensor as recited in claim 1, wherein the insulating layer is a TEOS (Tetraethoxysilane) layer.

Claim 4

A unit pixel in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a semiconductor layer of a first conductive type; a buried photodiode having a photo-sensing region formed in the semiconductor layer, for sensing light from an object and generating photoelectric charges; a floating junction of a second conductive type formed in the semiconductor layer, for receiving and storing the photoelectric charges from the buried photodiode; a transfer gate formed on the semiconductor layer between the floating junction and the buried photodiode; a drain junction of the second conductive type formed in the semiconductor layer; a reset gate formed on the semiconductor layer between the floating junction and the drain junction; a well region of the first conductive type formed in the semiconductor layer; drive and select gates formed on the well region with source/drain junctions; silicide layers formed on the floating junction, the transfer gate, the drain junction, the reset gate, the select gate and the source/drain junctions of the drive and select gates; and a plurality of insulating layer patterns which are provided by patterning an insulating layer, wherein the insulating layer patterns include; insulating spacers formed on sidewalls of the transfer, reset, drive and select gates; and a passivation layer formed on the photo-sensing region and on a sidewall of the transfer gate.

Claim 5

A unit pixel in a CMOS (Complementary Metal Oxide Semiconductor) image sensor, comprising: a semiconductor layer of a first conductive type; a buried photodiode having a photo-sensing region formed in the semiconductor layer, for sensing light from an object and generating photoelectric charges; a floating junction of a second conductive type formed in the semiconductor layer, for receiving and storing the photoelectric charges from the buried photodiode; a transfer gate formed on the semiconductor layer between the floating junction and the buried photodiode; a drain junction of the second conductive type formed in the semiconductor layer; a reset gate formed on the semiconductor layer between the floating junction and the drain junction; a well region of the first conductive type formed in the semiconductor layer; drive and select gates formed on the well region with source/drain junctions; silicide layers formed on the floating junction, the transfer gate, the drain junction, the reset gate, the select gate and the source/drain junctions of the drive and select gates; and a plurality of insulating layer patterns which are provided by patterning an insulating layer, wherein the insulating layer patterns include; insulating spacers formed on sidewalls of the transfer, reset, drive and select gates; and a passivation layer formed on the photo-sensing region and on a sidewall of the transfer gate.

Claim 6

The unit pixel as recited in claim 3, wherein the transfer and reset gates have channel length more than approximately 1 μm and the drive and select gates have channel length less than approximately 0.5 μm.

Claim 7

The unit pixel as recited in claim 3, wherein the insulating layer is a TEOS (Tetraethoxysilane) layer.