Clock distribution circuit in a semiconductor integrated circuit

Claim 1

A clock distribution circuit, to be used in a semiconductor integrated circuit having a plurality of interconnected cells arranged on a chip mounted on a substrate, for remotely distributing an externally applied clock signal to each of a plurality of clocked-circuit cells, each of which has a clock input terminal, so as to synchronize operations of the plural clocked-circuit cells, said clock distribution circuit comprising: an initial-stage driver disposed in the chip and connected to said externally applied clock signal; said initial-stage driver having a clock output terminal for sending said externally applied clock signal; a plurality of final-stage drivers disposed in the chip and each connected to at least one of the plural clocked-circuit cells, each said final-stage driver having a clock input terminal for receiving a clock signal from said initial stage driver to be provided to the corresponding clocked-circuit cell; a first clock wiring pattern, disposed in the chip and interconnecting between the clock output terminal of said initial-stage driver and the clock input terminals of said final-stage drivers, for distributing said clock signal from said initial-stage driver to the individual final-stage driver; a second clock wiring pattern disposed on the substrate and having a lower resistance than said first clock wiring pattern; and means for interconnecting between said first clock wiring pattern and said second clock wiring pattern at a plurality of points between said initial-stage driver and each of said plural final-stage drivers such that said first clock wiring pattern and said second clock wiring pattern extend in parallel.