Current-controlled output buffer

Claim 2

A current-controlled output buffer circuit having an input and an output, comprising: a control circuit having a control signal input port, a charging signal output port, and a discharging signal output port; a charging circuit having a charging signal input coupled to said charging signal output port, said charging circuit configured to supply a variable charging current to the buffer output in response to a charging signal on said charging signal input port, the magnitude of said variable charging current setting a signal rise time at the buffer output; and a discharging circuit having a discharging signal input coupled to said discharging signal output port, said discharging circuit configured to sink a variable discharging current from the buffer output in response to a discharging signal on said discharging signal input, the magnitude of said variable discharging current setting a signal fall time at the buffer output, wherein said signal rise time can be adjusted independently of said signal fall time.

Claim 3

The current-controlled output buffer circuit of claim 1, wherein said control circuit comprises a first current mirror coupled to said control signal input port, said first current mirror having a discharging signal current output and a charging signal current output.

Claim 4

The current-controlled output buffer circuit of claim 2, wherein said charging circuit comprises: a first adjustable current source having an input coupled to said charging current output of said first current mirror and an output, said first adjustable current source configured to generate a first reference current in response to a charging current signal on said charging current output; and a charging output stage coupled to said first adjustable current source output, said charging output stage configured to supply said charging current to said buffer output in response to said first reference current.

Claim 5

The current-controlled output buffer circuit of claim 3, wherein said first adjustable current source comprises: a second current mirror having a first port coupled to receive said charging current output of said first current mirror and a second port, said second current mirror configured to supply an intermediate current at said second port in response to said charging current signal; and a third current mirror having an input coupled to said second current mirror output and an output coupled to said charging output stage, said third current mirror configured to sink said first reference current in response to sinking said intermediate current from said second current mirror.

Claim 6

The current-controlled output buffer circuit of claim 4, wherein said charging output stage comprises: a fourth current mirror configured to supply said first reference current to said third current mirror; and a charging transistor coupled to said fourth current mirror, wherein said fourth current mirror controls said charging transistor to supply said charging current to said output buffer in response to said charging stage supplying said first reference current to said third current mirror.

Claim 7

The current-controlled output buffer circuit of claim 5, wherein said charging circuit further comprises a switching transistor having a gate terminal coupled to a signal input terminal, a source terminal coupled to a high supply, and a drain terminal coupled to a gate terminal of said charging transistor.

Claim 8

The current-controlled output buffer circuit of claim 2, wherein said charging circuit comprises: a second adjustable current source having an input coupled to said discharging current output of said first current mirror and an output, said second adjustable current source configured to generate a second reference current in response to a discharging current signal on said discharging current output; and a discharging output stage coupled to said second adjustable current source output, said discharging output stage configured to sink said discharging current to said output buffer in response to supplying said second reference current to said second adjustable current source.

Claim 9

The current-controlled output buffer circuit of claim 7, wherein said second adjustable current source comprises a fifth current mirror having an input coupled to said discharging current output of said first current mirror and an output, said fifth current mirror configured to supply said second reference current to said discharging output stage in response to supplying said discharging signal current to said first current mirror.

Claim 10

The current-controlled output buffer circuit of claim 4, wherein said discharging output stage comprises: a sixth current mirror configured to sink said second reference current from said fifth current mirror; and a discharging transistor coupled to said sixth current mirror, wherein said sixth current mirror controls said discharging transistor to sink said discharging current from said output buffer in response to said discharging output stage sinking said second reference current from said fifth current mirror.

Claim 11

The current-controlled output buffer circuit of claim 9, wherein said discharging circuit further comprises a switching transistor having a gate terminal coupled to a signal input terminal, a source terminal coupled to a low supply, and a drain terminal coupled to a gate terminal of said discharging transistor.

Claim 12

The current-controlled output buffer circuit of claim 2, wherein said first current mirror comprises: a first FET having a gate terminal and a drain terminal coupled to said control signal input port and a source terminal coupled to a low supply; a second FET having a gate terminal coupled to said gate terminal of said first FET, a drain terminal coupled to said charging signal port, and a source terminal coupled to said low supply; and a third FET having a gate terminal coupled to said gate terminal of said first FET, a drain terminal coupled to said discharging signal output port, and a source terminal coupled to said low supply.

Claim 13

The current-controlled output buffer circuit of claim 11, wherein said control circuit further comprises a fourth FET having a gate terminal coupled to a signal input terminal, a source terminal coupled to a high supply, and a drain terminal; a fifth FET having a gate terminal coupled to said gate terminal of said fourth FET, a drain terminal coupled to said drain terminal of said fourth FET, and a source terminal coupled to said low supply; a sixth FET having a gate terminal coupled to said drain terminal of said fourth FET, a source terminal coupled to said high supply, and a drain terminal; and a seventh FET having a gate terminal coupled to said drain terminal of said fifth FET, a drain terminal coupled to said drain terminal of said sixth FET, and a source terminal coupled to said low supply.

Claim 14

The current-controlled output buffer circuit of claim 4, wherein said second current mirror comprises: an eighth FET having a gate terminal and a drain terminal coupled together and a source terminal coupled to a high supply; a ninth FET having a gate terminal coupled to said gate terminal of said eighth FET, a source terminal coupled to said high supply, and a drain terminal coupled to said third current mirror; and a tenth FET having a gate terminal coupled to said signal input, a source terminal coupled to said high supply voltage, and a drain terminal coupled to said gate terminals of said eighth and ninth FETS.

Claim 15

The current-controlled output buffer circuit of claim 4, wherein said third current mirror comprises: an eleventh FET having a gate terminal and a drain terminal coupled together and to said second current mirror and a source terminal coupled to said low supply; and a twelfth FET having a gate terminal coupled to said gate terminal of said eleventh FET, a source terminal coupled to said low supply, and a drain terminal coupled to said charging output stage.

Claim 16

The current-controlled output buffer circuit of claim 4, wherein said third current mirror comprises: a first cascode FET pair comprising: a thirteenth FET having a gate terminal and a drain terminal coupled together and to said second current mirror and a source terminal; a fourteenth FET having a gate terminal coupled to said high supply, a drain terminal coupled to said source terminal of said thirteenth FET, and a source terminal coupled to said low supply; a second cascode FET pair comprising: a fifteenth FET having a gate terminal coupled to said gate terminal of said thirteenth FET, a drain terminal coupled to said output charging stage, and a source terminal; a sixteenth FET having a gate terminal coupled to said high supply, a drain terminal coupled to said source terminal of said fifteenth FET, and a source terminal coupled to said low supply; a third cascode FET pair comprising: a seventeenth FET having a gate terminal coupled to said gate terminal of said thirteenth FET, a drain terminal coupled to said output charging stage, and a source terminal; an eighteenth FET having a gate terminal, a drain terminal coupled to said output charging stage, and a source terminal coupled to said low supply; and a fourth cascode FET pair comprising: a nineteenth FET having a gate terminal coupled to said gate terminal of said thirteenth FET, a drain terminal coupled to said output charging stage, and a source terminal; and an twentieth FET having a gate terminal, a drain terminal coupled to said source terminal of said seventeenth FET, and a source terminal coupled to said low supply.

Claim 17

The current-controlled output buffer circuit of claim 8, wherein said fifth current mirror comprises: an twenty-first FET having a gate terminal and a drain terminal coupled together and a source terminal coupled to a high supply; a twenty-second FET having a gate terminal coupled to said gate terminal of said eighth FET, a source terminal coupled to said high supply, and a drain terminal coupled to said third current mirror; and a twenty-third FET having a gate terminal coupled to said drain terminal of said fourth FET, a source terminal coupled to said high supply voltage, and a drain terminal coupled to said gate terminals of said twenty-first and twenty-second FETs.

Claim 20

The method of claim 17 further comprising the steps of: turning off the first current mirror circuit when performing the sinking step; and turning off the second current mirror circuit when performing the supplying step.

Claim 21

An output buffer circuit for driving an output terminal, comprising: a charging output transistor coupled to the output terminal; a discharging output transistor coupled to the output termiinal; a first variable current source coupled to the charging output transistor and configured to vary a charging current of the charging output transistor in response to a first control signal; a second variable current source coupled to the discharging output transistor and configured to vary a discharging current of the discharging output transistor in response to a second control signal; and a control circuit coupled to the first and second variable current sources, and configured to generate the first and second control signals.

Claim 22

An output buffer circuit for driving an output terminal, comprising: a charging output transistor coupled to the output terminal; a discharging output transistor coupled to the output termiinal; a first variable current source coupled to the charging output transistor and configured to vary a charging current of the charging output transistor in response to a first control signal; a second variable current source coupled to the discharging output transistor and configured to vary a discharging current of the discharging output transistor in response to a second control signal; and a control circuit coupled to the first and second variable current sources, and configured to generate the first and second control signals.

Claim 23

The output buffer circuit of claim 19 further comprising: a first switch coupled to the charging output transistor; and a second switch coupled to the discharging output transistor, wherein, the first and second switches operate to turn one of the charging and discharging output transistors on and the other one off in response to an input signal.