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Patent US6037664A successfully refreshed from Google Patents.
US6037664A
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Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-03-31
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Granted: 2000-03-14
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Expires: 2018-03-31
Abstract
Abstract A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-ε) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-ε ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.
Inventors
- 👤 Bin Zhao
- 👤 Prahalad K. Vasudev
- 👤 Ronald S. Horwath
- 👤 Thomas E. Seidel
- 👤 Peter M. Zeitzoff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:57
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/037; H10W20/071; H10W20/081; H10W20/084; H10W20/086; H10W20/40; H10W20/41; H10W20/42; H10W20/425; H10W20/45; H10W20/48; Y; Y10; Y10S; Y10S438/00; Y10S438/902
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
285 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising: an underlying dielectric layer, a conductive region comprising deposited copper formed in said underlying dielectric layer, said conductive region having an upper surface, a conductive barrier/encapsulation layer selectively formed over said conductive region upper surface, a first inter-level dielectric ("ILD") layer formed over said conductive barrier/encapsulation layer and said first dielectric layer, said first ILD layer comprising low-ε material having a dielectric constant of less than 4, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material having a dielectric constant of less than 4, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first ILD layer and said first capping layer to the surface of said conductive barrier/encapsulation layer, a trench opening extending through said second ILD layer and said second capping layer, and connecting with said via opening, a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings, said conductive adhesion/barrier layer connecting to said conductive barrier/encapsulation layer and extending to the top of said second capping dielectric layer; continuous copper material filling the volume defined by said conductive adhesion/barrier layer and having a top surface; and a conductive barrier/encapsulation layer selectively formed over and capping said top surface of said continuous copper material, said conductive barrier/encapsulation layer joining with said conductive adhesion/barrier layer thus to fully encapsulate said continuous copper material.
Claim 2
Dependent Claim
285 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising: an underlying dielectric layer, a conductive region comprising deposited copper formed in said underlying dielectric layer, said conductive region having an upper surface, a conductive barrier/encapsulation layer selectively formed over said conductive region upper surface, a first inter-level dielectric ("ILD") layer formed over said conductive barrier/encapsulation layer and said first dielectric layer, said first ILD layer comprising low-ε material having a dielectric constant of less than 4, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material having a dielectric constant of less than 4, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first ILD layer and said first capping layer to the surface of said conductive barrier/encapsulation layer, a trench opening extending through said second ILD layer and said second capping layer, and connecting with said via opening, a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings, said conductive adhesion/barrier layer connecting to said conductive barrier/encapsulation layer and extending to the top of said second capping dielectric layer; continuous copper material filling the volume defined by said conductive adhesion/barrier layer and having a top surface; and a conductive barrier/encapsulation layer selectively formed over and capping said top surface of said continuous copper material, said conductive barrier/encapsulation layer joining with said conductive adhesion/barrier layer thus to fully encapsulate said continuous copper material.
Claim 3
Dependent Claim
22 words
The integrated circuit of claim 1, wherein said low-ε material of said first and said second ILD layers is an organic material.
Claim 4
Dependent Claim
26 words
The integrated circuit of claim 2, wherein said low-ε organic material is selected from the group consisting of polyimide, fluorinated polyimide, parylene, poly-arylethers, and fluorinated poly-arylethers.
Claim 5
Dependent Claim
27 words
The integrated circuit of claim 3, wherein the thickness of said first and said second ILD layers is in a range of from 5,000 to 10,000 angstroms.
Claim 6
Dependent Claim
18 words
The integrated circuit of claim 1, wherein the composition of said conductive barrier/encapsulation layers comprises cobalt tungsten phosphide.
Claim 7
Dependent Claim
24 words
The integrated circuit of claim 5, wherein the thickness of said conductive barrier/encapsulation layers is in a range of from 300 to 1000 angstroms.
Claim 8
Dependent Claim
14 words
The integrated circuit of claim 1, wherein said conductive adhesion/barrier layer is metallic material.
Claim 9
Dependent Claim
30 words
The integrated circuit of claim 7, wherein the composition of said conductive adhesion/barrier layer is selected from the group consisting of Ti, TiN, Ta, TaN, W, WN, SiN, and WSiN.
Claim 10
Dependent Claim
22 words
The integrated circuit of claim 1, wherein the composition of said first and said second capping dielectric layers comprises SiO 2 .
Claim 11
Dependent Claim
28 words
The integrated circuit of claim 9, wherein the thickness of said first and said second capping dielectric layers is in a range of from 300 to 1000 angstroms.
Claim 12
Dependent Claim
278 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising: an underlying dielectric layer having an upper surface, a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface, a first dielectric separation/barrier layer formed on said upper surfaces of said dielectric layer and said conductive region, a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-ε material having a dielectric constant of less than 4, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material having a dielectric constant of less than 4, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first capping layer, said first ILD layer and said first dielectric separation/barrier layer to said upper surface of said conductive region, a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening, a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region; continuous conductive material filling the volume defined by said conductive adhesion/barrier layer; and a second dielectric separation/barrier layer formed over said second capping dielectric layer and said continuous conductive material, said second dielectric separation/barrier layer in conjunction with said conducting barrier layer thus fully encapsulating said continuous conductive material.
Claim 13
Dependent Claim
278 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, and the interconnect conductors are fully encapsulated, said integrated circuit comprising: an underlying dielectric layer having an upper surface, a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface, a first dielectric separation/barrier layer formed on said upper surfaces of said dielectric layer and said conductive region, a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-ε material having a dielectric constant of less than 4, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material having a dielectric constant of less than 4, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first capping layer, said first ILD layer and said first dielectric separation/barrier layer to said upper surface of said conductive region, a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening, a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region; continuous conductive material filling the volume defined by said conductive adhesion/barrier layer; and a second dielectric separation/barrier layer formed over said second capping dielectric layer and said continuous conductive material, said second dielectric separation/barrier layer in conjunction with said conducting barrier layer thus fully encapsulating said continuous conductive material.
Claim 14
Dependent Claim
12 words
The integrated circuit of claim 11, wherein said conductive region comprises copper.
Claim 15
Dependent Claim
12 words
The integrated circuit of claim 11, wherein said conductive region comprises aluminum.
Claim 16
Dependent Claim
14 words
The integrated circuit of claim 11, wherein said conductive region is a doped region.
Claim 17
Dependent Claim
13 words
The integrated circuit of claim 11, wherein said continuous conductive material is copper.
Claim 18
Dependent Claim
13 words
The integrated circuit of claim 11, wherein said continuous conductive material is aluminum.
Claim 19
Dependent Claim
22 words
The integrated circuit of claim 11, wherein said low-ε material of said first and said second ILD layers is an organic material.
Claim 20
Dependent Claim
26 words
The integrated circuit of claim 17, wherein said low-ε organic material is selected from the group consisting of polyimide, fluorinated polyimide, parylene, poly-arylethers, and fluorinated poly-arylethers.
Claim 21
Dependent Claim
27 words
The integrated circuit of claim 11, wherein the thickness of said first and said second ILD layers is in a range of from 5,000 to 10,000 angstroms.
Claim 22
Dependent Claim
14 words
The integrated circuit of claim 11, wherein said adhesion/barrier layer is a metallic material.
Claim 23
Dependent Claim
27 words
The integrated circuit of claim 11, wherein said adhesion/barrier layer comprises materials selected from the group consisting of Ti, TiN, Ta, TaN, W, WN, SiN, and WSiN.
Claim 24
Dependent Claim
34 words
The integrated circuit of claim 11, wherein the composition of said first and said second capping dielectric layers is selected to have an etch characteristic different from that of said first dielectric separation/barrier layer.
Claim 25
Dependent Claim
22 words
The integrated circuit of claim 11, wherein said composition of said first and said second capping dielectric layers is SiO 2 .
Claim 26
Dependent Claim
17 words
The integrated circuit of claim 11, wherein said first and said second dielectric separation/barrier layers are SiN.
Claim 27
Dependent Claim
26 words
The integrated circuit of claim 11, wherein the thickness of said first and said second capping dielectric layers is in a range of from 300-1000 angstroms.
Claim 28
Dependent Claim
208 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, said integrated circuit comprising: an underlying dielectric layer having an upper surface, a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface, a first dielectric separation/barrier layer formed on said upper surfaces of said underlying dielectric layer and said conductive region, a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-ε material, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first capping layer, said first ILD layer, and said first dielectric separation/barrier layer to said upper surface of said conductive region, a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening, and a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region.
Claim 29
Dependent Claim
208 words
An integrated circuit formed on a semiconductor substrate having an interconnect structure formed thereon, in which dual dielectric layers of low-ε material are utilized for fabricating the interconnect structure, said integrated circuit comprising: an underlying dielectric layer having an upper surface, a conductive region formed in said underlying dielectric layer, said conductive region having an upper surface, a first dielectric separation/barrier layer formed on said upper surfaces of said underlying dielectric layer and said conductive region, a first inter-level dielectric ("ILD") layer formed over said first dielectric separation/barrier layer and comprising low-ε material, a first capping dielectric layer formed over said first ILD layer, a second ILD layer formed over said first capping dielectric layer and comprising low-ε material, a second capping dielectric layer formed over said second ILD layer, a via opening extending through said first capping layer, said first ILD layer, and said first dielectric separation/barrier layer to said upper surface of said conductive region, a trench opening extending through said second ILD layer and said second capping dielectric layer, and connecting with said via opening, and a conductive adhesion/barrier layer formed on the inner surfaces defined by said via and said trench openings and extending through said dielectric separation/barrier layer to contact said conductive region.
References Cited (Backward Citations)
US5741626A
Cited
US5695810A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |