US6035393A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution
Assignee: Intel Corp
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Filing: 1998-05-07
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Granted: 2000-03-07
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Expires: 2018-05-07
Abstract
Abstract A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction prefetch, an instruction fetch unit (IFU) receives an instruction pointer indicating a memory location containing an instruction to be prefetched. The instruction pointer may be provided by a branch target buffer (BTB) as a result of a branch prediction, or by auxiliary branch prediction mechanisms, or actual execution. The IFU accesses an instruction translation look-aside buffer (ITLB) to determine both the physical address corresponding to the linear address of the instruction pointer and to determine an associated memory type stored therein. If the memory type indicates an uncacheable memory location, the IFU waits until all previous executed instructions have completed. The IFU does this by inserting a "permission-to-fetch" instruction, and then stalling. The IFU remains stalled until either the permission-to-fetch instruction retires or until a branch misprediction is detected. Once a branch misprediction is detected, the permission-to-fetch instruction and all other instructions issued subsequent to the mispredicted branch are squashed. If no previous branch mispredictions are detected, the permission-to-fetch instruction eventually retires, the instruction pointer is reset based on the correct branch, and prefetching continues.
Inventors
- 👤 Andrew F. Glew
- 👤 Ashwani Gupta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292; G06F9/3861; G06F2212/00; G06F2212/20; G06F2212/206
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
74 words
A method of operating a microprocessor comprising the steps of: (a) predicting a direction of an instruction path; (b) identifying a memory location containing an instruction within the instruction path; (c) determining whether the memory location is cacheable; if so, (d) prefetching the instruction from the memory location; otherwise, (e) dispatching a dummy instruction; and (f) stalling prefetching operations until either the dummy instruction retires, or a misprediction of a previous branch is detected.
Claim 2
Independent Claim
74 words
A method of operating a microprocessor comprising the steps of: (a) predicting a direction of an instruction path; (b) identifying a memory location containing an instruction within the instruction path; (c) determining whether the memory location is cacheable; if so, (d) prefetching the instruction from the memory location; otherwise, (e) dispatching a dummy instruction; and (f) stalling prefetching operations until either the dummy instruction retires, or a misprediction of a previous branch is detected.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein step (a) comprises the step of performing a static prefetch prediction.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein step (a) comprises performing a branch prediction.
Claim 5
Dependent Claim
30 words
The method of claim 1 wherein step (c) comprises the step of examining a memory type associated with the instruction, the memory type identifying the cacheability of the memory location.
Claim 6
Dependent Claim
38 words
The method of claim 4 wherein the step of examining the memory type value includes the step of accessing an instruction translation look-aside buffer storing internal addresses, physical addresses and associated memory types for a plurality of instructions.
Claim 7
Dependent Claim
28 words
The method of claim 5 further comprising the step of initiating a page table walk in the event that the translation look-aside buffer access results in a miss.
Claim 8
Dependent Claim
56 words
The method of claim 1, wherein if the misprediction is detected, the method further comprising the steps of: squashing the dummy instruction and all other instructions subsequent to the previous branch; resetting an instruction pointer based on a correct branch; and repeating steps (d)-(f), with the instruction pointer specifying a memory location of a new instruction.
Claim 9
Dependent Claim
25 words
The method of claim 1 wherein if the dummy instruction retires, the method further comprising the step of: prefetching the instruction from the memory location.
Claim 10
Dependent Claim
138 words
A microprocessor that performs operations either out-of-order or speculatively comprising: a memory; means for predicting a direction of an instruction path for a program which includes an ordered sequence of instructions; means for identifying a memory type of a location in the memory storing an instruction within the ordered sequence, the memory type indicating the cacheability of a region of the memory which contains the location; means for prefetching instructions in the ordered sequence, the prefetching means being coupled to the identifying means to access the memory type of the location storing the instruction prior to prefetching the instruction, in the event that the memory type indicates an uncacheable region, the prefetching means stalling until either a misprediction of a previous branch is detected, or a signal is received assuring that a previous branch misprediction has not occurred.
Claim 11
Dependent Claim
138 words
A microprocessor that performs operations either out-of-order or speculatively comprising: a memory; means for predicting a direction of an instruction path for a program which includes an ordered sequence of instructions; means for identifying a memory type of a location in the memory storing an instruction within the ordered sequence, the memory type indicating the cacheability of a region of the memory which contains the location; means for prefetching instructions in the ordered sequence, the prefetching means being coupled to the identifying means to access the memory type of the location storing the instruction prior to prefetching the instruction, in the event that the memory type indicates an uncacheable region, the prefetching means stalling until either a misprediction of a previous branch is detected, or a signal is received assuring that a previous branch misprediction has not occurred.
Claim 12
Dependent Claim
12 words
The microprocessor of claim 9 wherein the memory comprises an instruction cache.
Claim 13
Dependent Claim
21 words
The microprocessor of claim 10 wherein the means for predicting the direction of the instruction path comprises a branch target buffer.
Claim 14
Dependent Claim
15 words
The microprocessor of claim 11 wherein the identifying means comprises an instruction translation look-aside buffer.
Claim 15
Dependent Claim
32 words
The microprocessor of claim 12 further comprising a means for providing an instruction pointer to the prefetching means, the instruction pointer indicating a next instruction to be prefetched in the ordered sequence.
Claim 16
Dependent Claim
63 words
The microprocessor of claim 13, further comprising; means for predicting a target of a branch instruction and for subsequently determining whether the target is a mispredicted branch; means for issuing a dummy instruction in the event that the memory type of the location storing the instruction indicates an uncacheable memory region; and means for producing the signal upon retirement of the dummy instruction.
Claim 17
Dependent Claim
130 words
A microprocessor that performs operations either out-of-order or speculatively comprising: a branch target buffer to predict a direction of an instruction path for a program; an instruction translation look-aside buffer to determine a physical address and a memory type corresponding to a linear address of an instruction to be prefetched, the memory type indicating the cacheability of the instruction; an instruction fetch unit to prefetch instructions in the program, the instruction fetch unit accessing the instruction translation look-aside buffer to determine the memory type of the instruction to be prefetched; when the memory type indicates that the instruction is in an uncacheable memory region the instruction fetch unit dispatches a dummy instruction and then stalls until either a misprediction of a previous branch is detected or the dummy instruction retires.
Claim 18
Dependent Claim
130 words
A microprocessor that performs operations either out-of-order or speculatively comprising: a branch target buffer to predict a direction of an instruction path for a program; an instruction translation look-aside buffer to determine a physical address and a memory type corresponding to a linear address of an instruction to be prefetched, the memory type indicating the cacheability of the instruction; an instruction fetch unit to prefetch instructions in the program, the instruction fetch unit accessing the instruction translation look-aside buffer to determine the memory type of the instruction to be prefetched; when the memory type indicates that the instruction is in an uncacheable memory region the instruction fetch unit dispatches a dummy instruction and then stalls until either a misprediction of a previous branch is detected or the dummy instruction retires.
Claim 19
Dependent Claim
38 words
The microprocessor of claim 15 further comprising a reorder buffer that transmits a signal to the instruction fetch unit indicating that the dummy instruction has retired, the instruction fetch unit fetching the instruction in response to the signal.
Claim 20
Dependent Claim
45 words
The microprocessor of claim 15 further comprising an instruction cache, the instruction fetch unit first accessing the instruction cache to determine whether the instruction is already contained therein; if not, the instruction fetch unit generating a request to an external memory to load the instruction.
Claim 21
Dependent Claim
25 words
The microprocessor of claim 15, wherein if the misprediction is detected the microprocessor squashes all instructions dispatched following the previous branch, including the dummy instruction.
Claim 22
Dependent Claim
51 words
The microprocessor of claim 15, further comprising an instruction pointer issued to the instruction fetch unit to specify the linear address of the instruction to be prefetched, wherein the instruction pointer may be issued in response to a branch prediction of the branch target buffer or detection of a mispredicted branch.
Claim 23
Dependent Claim
17 words
The microprocessor of claim 15, wherein only a single dummy instruction is pending at any given time.
Claim 24
Dependent Claim
20 words
The microprocessor of claim 15, wherein the dummy instruction includes an opcode indicating the relative age of the dummy instruction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |