Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions

Claim 3

The method of claim 1 further comprising the step of: aborting said speculative page table walk in the event that said PDE and PTE loads access non-speculateable memory locations.

Claim 4

The method of claim 2 further comprising the step of: aborting said speculative page table walk in the event that a memory ordering violation occurs.

Claim 5

The method of claim 2 wherein said aborting step comprises the step of: re-dispatching said memory instruction with a non-speculateable designation; and deferring execution of said re-dispatched memory instruction until retirement of said memory instruction.

Claim 6

The method of claim 1 further comprising the step of: in response to a page fault, deferring said speculative page table walk until said page fault has been resolved.

Claim 7

The method of claim 1 further comprising the steps of: aborting said speculative page table walk; re-dispatching said memory instruction with a non-speculateable designation; dispatching instructions which control performance of a non-speculative page table walk and setting of an access bid or a dirty bit.

Claim 8

In a microprocessor which speculatively executes instructions having an identification value, said microprocessor including a reservation station (RS) for allocating and dispatching said instructions, a re-order buffer (ROB) for re-ordering and retiring said instructions, a memory ordering buffer (MOB) for ordering the execution of memory instructions, a data cache unit (DCU) for caching data subject to said memory instructions, a translation lookaside buffer (TLB) for caching physical addresses and corresponding linear addresses for selected data locations, and a page miss handler (PMH) which performs page table walks to determine said physical addresses corresponding to said linear addresses of a memory instruction, a method of operation comprising the steps of: dispatching a speculative memory instruction from said RS, said speculative memory instruction including a linear address defining a physical address location, said linear address missing said TLB; performing a speculative page table walk to determine said physical address corresponding to said linear address, said speculative page table walk including the steps of: dispatching page directory entry (PDE) and page table entry (PTE) loads which do not have said identification value, said PDE and PTE loads accessing speculateable memory; fetching data associated with said PDE and PTE loads; loading said physical address into said TLB in response to said fetching step.

Claim 9

In a microprocessor which speculatively executes instructions having an identification value, said microprocessor including a reservation station (RS) for allocating and dispatching said instructions, a re-order buffer (ROB) for re-ordering and retiring said instructions, a memory ordering buffer (MOB) for ordering the execution of memory instructions, a data cache unit (DCU) for caching data subject to said memory instructions, a translation lookaside buffer (TLB) for caching physical addresses and corresponding linear addresses for selected data locations, and a page miss handler (PMH) which performs page table walks to determine said physical addresses corresponding to said linear addresses of a memory instruction, a method of operation comprising the steps of: dispatching a speculative memory instruction from said RS, said speculative memory instruction including a linear address defining a physical address location, said linear address missing said TLB; performing a speculative page table walk to determine said physical address corresponding to said linear address, said speculative page table walk including the steps of: dispatching page directory entry (PDE) and page table entry (PTE) loads which do not have said identification value, said PDE and PTE loads accessing speculateable memory; fetching data associated with said PDE and PTE loads; loading said physical address into said TLB in response to said fetching step.

Claim 10

The method of claim 7 further comprising the steps of: transmitting a signal from said MOB to said PMH which causes said PMH to abort said page table walk if a store to said physical address location is older than said speculative memory instruction; re-dispatching said speculative memory instruction; and executing said re-dispatched speculative memory instruction following retirement of said speculative memory instruction.

Claim 11

The method of claim 7, further comprising the steps of: aborting said speculative page table walk; waiting until said speculative memory instruction retires; and executing micro-code instructions which cause said PMH to perform a non-speculative page table walk; and setting an access bit or a dirty bit.

Claim 14

The apparatus of claim 10, further including: memory ordering buffer (MOB) means for storing and re-ordering memory instructions, said MOB means responding to instructions irrespective of said valid identification value; and wherein said means for performing said speculative page table walk further includes: means for ordering said PDE and PTE loads within said MOB and for detecting memory ordering violations; and means for aborting said page table walk in response to a memory ordering violation.

Claim 15

The apparatus of claim 11, wherein said means for aborting said page table walk includes means for re-dispatching said memory instruction from said PMH with a non-speculateable designation.

Claim 16

The apparatus of claim 10, further comprising: a data cache unit (DCU) means for retrieving data subject to a memory instruction.

Claim 17

The apparatus of claim 13, further including means for detecting a page fault condition.

Claim 18

The apparatus of claim 11, further including: means for dispatching micro-code instructions which cause an access bit or a dirty bit to be set for a corresponding page of memory.

Claim 19

The apparatus of claim 10, further including: means for updating said TLB with said physical address determined during said page table walk.

Claim 20

A microprocessor comprising: an out-of-order engine which generates memory instructions having linear addresses; reservation station that allocates and dispatches instructions having a valid identification value; re-ordering buffer that reorders and retires speculative instructions having a valid identification value; a translation lookaside buffer (TLB) which caches linear addresses and corresponding physical addresses; and a page-miss handler (PMH) that performs a page table walk to determine a physical address corresponding to a linear address, said PMH determining whether a memory instruction causing a TLB miss is a speculative memory instruction, and performing a non-speculative page table walk, if the memory instruction is non-speculative, and performing a speculative page table walk, if said memory instruction is speculative.

Claim 21

A microprocessor comprising: an out-of-order engine which generates memory instructions having linear addresses; reservation station that allocates and dispatches instructions having a valid identification value; re-ordering buffer that reorders and retires speculative instructions having a valid identification value; a translation lookaside buffer (TLB) which caches linear addresses and corresponding physical addresses; and a page-miss handler (PMH) that performs a page table walk to determine a physical address corresponding to a linear address, said PMH determining whether a memory instruction causing a TLB miss is a speculative memory instruction, and performing a non-speculative page table walk, if the memory instruction is non-speculative, and performing a speculative page table walk, if said memory instruction is speculative.

Claim 22

The apparatus of claim 17, wherein said PMH comprises: means for dispatching page directory entry (PDE) and page table entry (PTE) loads, said PDE and PTE loads lacking said valid identification value; wherein said ROB and said RS are non-responsive to said PDE and PTE loads during said speculative page table walk.

Claim 23

The apparatus of claim 17, further including: means for storing and re-ordering memory instructions, said buffer means ordering said PDE and PTE loads relative to other loads and detecting a memory ordering violation; and; means for aborting said page table walk responsive to said memory ordering violation.

Claim 24

The apparatus of claim 19, wherein said dispatching means re-dispatches said memory instruction with a non-speculateable designation, execution of said re-dispatched memory instruction being deferred by said buffer means until retirement.

Claim 25

The apparatus of claim 19, further including: a data cache unit (DCU) that stores data associated with said memory instruction.

Claim 26

The apparatus of claim 21 wherein said DCU includes means for detecting page fault conditions; and said dispatching means re-dispatches said memory instruction with a non-speculateable designation upon detection of a page fault.

Claim 27

The apparatus of claim 17 wherein: said out-of-order engine includes means for dispatching micro-code PDE and PTE instructions which cause said PMH to perform said non-speculative page table walk and set an access bit or a dirty bit for selected pages of memory.

Claim 28

A microprocessor capable of out-of-order and speculative execution of instructions, comprising: out-of-order engine for generating instructions; a reservation station (RS) for storing instructions that have yet to be executed; a memory ordering buffer (MOB) for ordering the execution of memory instructions; a data cache unit (DCU) for caching data subject to the memory instructions; a translation lookaside buffer (TLB) for caching physical address and corresponding linear addresses for selected data locations; a page miss handler (PMH) for performing page walks for memory instructions to determine a physical address corresponding to a linear address, with said PMH capable of performing said page table walk speculatively; and a re-ordering buffer (ROB) for re-ordering and retiring instructions.

Claim 29

A microprocessor capable of out-of-order and speculative execution of instructions, comprising: out-of-order engine for generating instructions; a reservation station (RS) for storing instructions that have yet to be executed; a memory ordering buffer (MOB) for ordering the execution of memory instructions; a data cache unit (DCU) for caching data subject to the memory instructions; a translation lookaside buffer (TLB) for caching physical address and corresponding linear addresses for selected data locations; a page miss handler (PMH) for performing page walks for memory instructions to determine a physical address corresponding to a linear address, with said PMH capable of performing said page table walk speculatively; and a re-ordering buffer (ROB) for re-ordering and retiring instructions.

Claim 30

The apparatus of claim 24, wherein: said PMH determines whether an event has occurred preventing speculative determination of the physical address, aborts the page table walk upon the detection of said event, and sends a request through the TLB to the RS and MOB indicating said event.

Claim 31

The apparatus of claim 24, further including a memory bus connecting said RS, MOB, DCU, TLB and PMH; and wherein said memory instruction is a load defined by a micro-instruction (uOP), and wherein said MOB maintains a value uniquely identifying each pending uOP; and said PMH dispatches a stuffed load onto said memory bus, said stuffed load being a uOP having no associated value.

Claim 32

A computer system comprising: a plurality of microprocessors capable of speculative execution of instructions; an input/output unit; a memory; a system bus for interconnecting said microprocessors, said input/output unit and said memory; wherein each of said microprocessors includes an out-of-order engine for generating memory instructions having linear addresses; a reservation station for allocating and dispatching instructions having a valid identification value; a re-ordering buffer for reordering and retiring speculative instructions having a valid identification value; a translation lookaside buffer (TLB) for caching linear addresses and corresponding physical addresses; and a page-miss handler (PMH) for performing a page table walk to determine a physical address corresponding to a linear address not found in the TLB, said PMH determining whether the memory instruction causing the TLB miss is a speculative memory instruction and performing a non-speculative page table walk, if the memory instruction is non-speculative; and performing a speculative page table walk, if said memory instruction is speculative.

Claim 33

A computer system comprising: a plurality of microprocessors capable of speculative execution of instructions; an input/output unit; a memory; a system bus for interconnecting said microprocessors, said input/output unit and said memory; wherein each of said microprocessors includes an out-of-order engine for generating memory instructions having linear addresses; a reservation station for allocating and dispatching instructions having a valid identification value; a re-ordering buffer for reordering and retiring speculative instructions having a valid identification value; a translation lookaside buffer (TLB) for caching linear addresses and corresponding physical addresses; and a page-miss handler (PMH) for performing a page table walk to determine a physical address corresponding to a linear address not found in the TLB, said PMH determining whether the memory instruction causing the TLB miss is a speculative memory instruction and performing a non-speculative page table walk, if the memory instruction is non-speculative; and performing a speculative page table walk, if said memory instruction is speculative.