Solid-state memory device

Claim 1

A semiconductor storage device, comprising: a semiconductor substrate; bit lines disposed on said semiconductor substrate; word lines disposed on said semiconductor substrate; a plurality of storage cells having data contents and disposed on said semiconductor substrate at intersections of and connected to said bit lines and said word lines; a word-line drive circuit connected to said word lines and a bit-line drive circuit connected to said bit lines for driving and programming said data contents of said plurality of storage cells; enable bit lines; an enable bit-line drive circuit connected to and driving said enable bit lines separately and independently of said bit-line drive circuit; enable storage cells disposed along said enable bit lines and driveable by said enable bit-line drive circuit, said enable storage cells assigned to said plurality of storage cells of said word lines and having enable values for enabling said plurality of storage cells of a predetermined word line, an m number of said enable bit lines provided for selectably reserving a number of 2 m program regions of said plurality of storage cells; a microprocessor outputting a control signal having a value; and a comparator having a first input connected to said enable bit lines and receiving said enable values and a second input receiving said control signal from said microprocessor, said comparator generating a comparator output signal if said value of said control signal and said enable values are unequal.