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US6034544A
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Programmable input/output block (IOB) in FPGA integrated circuits
Assignee: Lattice Semiconductor Corp
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Filing: 1997-12-22
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Granted: 2000-03-07
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Expires: 2017-12-22
Abstract
Abstract A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs) An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines.
Inventors
- 👤 Om P. Agrawal
- 👤 Herman M. Chang
- 👤 Bradley A. Sharpe-Geisler
- 👤 Bai Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
76 words
An input/output block (IOB) for a field programmable gate array (FPGA) device, comprising: (a) an input for receiving an input signal from a pin; (b) a register/latch, coupled to the input, having an output, for providing an output signal; and (c) a first transistor, coupled to the register/latch output, for providing a ground path for an inter-connect resource coupled to the IOB, wherein the inter-connect resource is coupled to a second IOB and a current source.
Claim 2
Dependent Claim
76 words
An input/output block (IOB) for a field programmable gate array (FPGA) device, comprising: (a) an input for receiving an input signal from a pin; (b) a register/latch, coupled to the input, having an output, for providing an output signal; and (c) a first transistor, coupled to the register/latch output, for providing a ground path for an inter-connect resource coupled to the IOB, wherein the inter-connect resource is coupled to a second IOB and a current source.
Claim 3
Dependent Claim
21 words
The IOB of claim 1, wherein the inter-connect resource is a line positioned substantially parallel to a side of the FPGA.
Claim 4
Dependent Claim
15 words
The IOB of claim 1, wherein a second transistor is coupled to the first transistor.
Claim 5
Dependent Claim
28 words
The IOB of claim 3, wherein the second transistor includes a gate coupled to a multiplexer and the first transistor includes a gate coupled to the register/latch output.
Claim 6
Dependent Claim
204 words
An input/output block (IOB) for a field programmable gate array (FPGA) device, comprising: (a) an input for receiving an input signal from a pin; (b) a delay element, coupled to the input, having an output for providing a delayed input signal; (c) a first multiplexer, coupled to the delay element, having an output for providing a first multiplexer signal responsive to the delayed input signal; (d) a second multiplexer, coupled to the first multiplexer, having an output for providing a second multiplexer signal responsive to the first multiplexer signal; (e) a register/latch, coupled to the second multiplexer, having an output for providing a register/latch output signal responsive to the second multiplexer signal, a set signal and a reset signal; (f) a set/reset line for providing a set/reset signal; (g) a decoder, coupled to the set/reset line, for providing the set signal or the reset signal responsive to the set/reset signal; (h) a third multiplexer, coupled to the register/latch output, having an output for providing a third multiplexer signal responsive to the register/latch output signal; and, (i) an amplifier, coupled to the third multiplexer, having an output for providing an amplified signal to an inter-connect resource in the FPGA responsive to the third multiplexer signal.
Claim 7
Dependent Claim
204 words
An input/output block (IOB) for a field programmable gate array (FPGA) device, comprising: (a) an input for receiving an input signal from a pin; (b) a delay element, coupled to the input, having an output for providing a delayed input signal; (c) a first multiplexer, coupled to the delay element, having an output for providing a first multiplexer signal responsive to the delayed input signal; (d) a second multiplexer, coupled to the first multiplexer, having an output for providing a second multiplexer signal responsive to the first multiplexer signal; (e) a register/latch, coupled to the second multiplexer, having an output for providing a register/latch output signal responsive to the second multiplexer signal, a set signal and a reset signal; (f) a set/reset line for providing a set/reset signal; (g) a decoder, coupled to the set/reset line, for providing the set signal or the reset signal responsive to the set/reset signal; (h) a third multiplexer, coupled to the register/latch output, having an output for providing a third multiplexer signal responsive to the register/latch output signal; and, (i) an amplifier, coupled to the third multiplexer, having an output for providing an amplified signal to an inter-connect resource in the FPGA responsive to the third multiplexer signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |