US6030884A
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Method of bonding a III-V group compound semiconductor layer on a silicon substrate
Assignee: NEC Corp
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Filing: 1997-12-15
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Granted: 2000-02-29
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Expires: 2017-12-15
Abstract
Abstract Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation layer, having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.
Inventors
- 👤 Kazuo Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:45
CPC Classifications
H; H10; H10P; H10P10/00; H10P10/12; H10P10/128; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
204 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer on said III-V group compound semiconductor layer; preparing a first contact layer of one of In and Sb on said intermediate layer; preparing a second contact layer of said one of In and Sb on said silicon layer; contacting said first and second contact layers together to form a bonding interface; and subjecting said intermediate, silicon, first and second contact layers, and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 2
Independent Claim
204 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer on said III-V group compound semiconductor layer; preparing a first contact layer of one of In and Sb on said intermediate layer; preparing a second contact layer of said one of In and Sb on said silicon layer; contacting said first and second contact layers together to form a bonding interface; and subjecting said intermediate, silicon, first and second contact layers, and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 3
Dependent Claim
69 words
The method as claimed in claim 1, wherein said strained semiconductor layer includes at least a semiconductor layer having a rigidity coefficient being sufficiently small to permit generation of crystal defects in said strained semiconductor layer by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 4
Independent Claim
171 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer wherein said strained semiconductor layer comprises a semiconductor material including sb.
Claim 5
Independent Claim
171 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer wherein said strained semiconductor layer comprises a semiconductor material including sb.
Claim 6
Dependent Claim
28 words
The method as claimed in claim 1, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different lattice constants from each other.
Claim 7
Dependent Claim
27 words
The method as claimed in claim 1, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different planes from each other.
Claim 8
Dependent Claim
31 words
The method as claimed in claim 1, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different crystal axes in tilted angle from each other.
Claim 9
Dependent Claim
31 words
The method as claimed in claim 1, wherein said strained semiconductor layer comprises a lamination of at least two semiconductor layers having different crystal axes in rotation direction from each other.
Claim 10
Dependent Claim
17 words
The method as claimed in claim 1, wherein said strained semiconductor layer comprises strained semiconductor super-lattice layers.
Claim 11
Independent Claim
179 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer; said strained semiconductor layer comprises strained semiconductor super-lattice layers; and said strained semiconductor super-lattice layers comprises InAlAs/InGaAs super-lattice layers.
Claim 12
Independent Claim
179 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer; said strained semiconductor layer comprises strained semiconductor super-lattice layers; and said strained semiconductor super-lattice layers comprises InAlAs/InGaAs super-lattice layers.
Claim 13
Independent Claim
265 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V grout compound semiconductor layer and said silicon layer; and wherein said first preparation step further includes the step of forming a thermal stress relaxation layer between said intermediate layer and said silicon layer, said thermal stress relaxation layer having a thermal expansion coefficient equal or near to the thermal expansion coefficient of said III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in said III-V group compound semiconductor layer due to a thermal stress generated in said heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 14
Independent Claim
265 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V grout compound semiconductor layer and said silicon layer; and wherein said first preparation step further includes the step of forming a thermal stress relaxation layer between said intermediate layer and said silicon layer, said thermal stress relaxation layer having a thermal expansion coefficient equal or near to the thermal expansion coefficient of said III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in said III-V group compound semiconductor layer due to a thermal stress generated in said heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer.
Claim 15
Dependent Claim
27 words
The method as claimed in claim 10, wherein said thermal stress relaxation layer comprises a semiconductor material including at least any one of Ge, Ga and Al.
Claim 16
Dependent Claim
19 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least a Ge layer.
Claim 17
Dependent Claim
20 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least an SiGe amorphous layer.
Claim 18
Dependent Claim
20 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least an Si/Ge superlattice layer.
Claim 19
Dependent Claim
19 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least an AlP layer.
Claim 20
Dependent Claim
19 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least a GaP layer.
Claim 21
Dependent Claim
19 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least an AlAs layer.
Claim 22
Dependent Claim
19 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least a GaAs layer.
Claim 23
Dependent Claim
38 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least a layer of amorphous semiconductors including at least two compound semiconductors selected from the group consisting of AlP, GaP, AlAs and GaAs.
Claim 24
Dependent Claim
42 words
The method as claimed in claim 11, wherein said thermal stress relaxation layer includes at least a superlattice layer of two kinds of compound semiconductor layers, said two compound semiconductors being selected from the group consisting of AlP, GaP, AlAs and GaAs.
Claim 25
Independent Claim
176 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer; and wherein said III-V group semiconductor layer includes at least any one of In and Sb.
Claim 26
Independent Claim
176 words
A method for bonding a III-V group compound semiconductor layer to a silicon layer, said III-V group compound semiconductor layer having a different thermal expansion coefficient from a thermal expansion coefficient of said silicon layer and having a different rigidity coefficient from a rigidity coefficient of said silicon layer, said method comprising the steps of: preparing an intermediate layer sandwiched between said silicon layer and said III-V group compound semiconductor layer; and subjecting said intermediate, silicon and III-V group compound semiconductor layers to a heat treatment at a temperature not less than 450° C.; wherein said intermediate layer comprises a strained semiconductor layer capable of preventing a threading dislocation to extend through said strained layer into said III-V group compound semiconductor layer, said threading dislocation being caused by a thermal stress generated in said heat treatment and subsequent cooling stage due to the difference in the thermal expansion coefficient between said III-V group compound semiconductor layer and said silicon layer; and wherein said III-V group semiconductor layer includes at least any one of In and Sb.
Claim 27
Dependent Claim
58 words
The method as claimed in claim 10, wherein said first preparation step further includes the step of forming at least a semiconductor contact layer between said thermal stress relaxation layer and said strained semiconductor layer, said semiconductor contact layer having a rigidity coefficient being sufficiently small for facilitating atomic re-arrangements in said contact layer by said heat treatment.
Claim 28
Dependent Claim
21 words
The method as claimed in claim 22, wherein said semiconductor contact layer includes at least any one of In and Sb.
Claim 29
Dependent Claim
46 words
The method as claimed in claim 10, wherein said first preparation step further includes the step of forming at least an insulation contact layer between said thermal stress relaxation layer and said strained semiconductor layer to permit a low temperature bonding with a static voltage application.
Claim 30
Dependent Claim
74 words
The method as claimed in claim 10, wherein said first preparation step comprises the steps of: forming said III-V group compound semiconductor layer on a supporting substrate made of the same compound semiconductors as said III-V group compound semiconductor layer; forming said strained semiconductor layer on said III-V group compound semiconductor layer; forming said thermal stress relaxation layer on said strained semiconductor layer; and contacting said thermal stress relaxation layer with said silicon layer.
References Cited (Backward Citations)
JPS61182215A
Cited
JPS61183918A
Cited
JPH01133341A
Cited
JPH01238113A
Cited
US4891329A
Cited
JPH02194519A
Cited
US5439843A
Cited
US5346848A
Cited
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